SIGDA E-News 1 February 2012, Vol. 42, No. 02

1 February 2012, Vol. 42, No. 2
Online archive: http://www.sigda.org/newsletter

SIGDA News
From: Lin Yuan <yuanl@synopsys.com>
What is Wireless On-Chip Interconnect?
    Contributing authors:
    Ankit More <am434@drexel.edu>, Baris Taskin <taskin@coe.drexel.edu>, Drexel University
    From: Srinivas Katkoori <katkoori@cse.usf.edu>
Paper Submission Deadlines
From: Debjit Sinha <debjitsinha@yahoo.com>
Upcoming Conferences and Symposia
From: Debjit Sinha <debjitsinha@yahoo.com>
Upcoming Funding Opportunities
From: Sudeep Pasricha <sudeep@colostate.edu>
Call for Papers: VLSI Design Journal Special Issue on New Algorithmic Techniques for EDA Problems
From: Shantanu Dutt <dutt@ece.uic.edu>
Call for Papers: TCAD Special Section on Three-dimensional Integrated Circuits and Microarchitectures
From: Deming Chen <dchen@illinois.edu>
Call for Papers: International Conference on Formal Methods and Models for Codesign (MEMOCODE)
From: Luca Carloni <luca@cs.columbia.edu>
Call for Papers: International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
From: Sudeep Pasricha <sudeep@colostate.edu>
Call for Papers: International Symposium on Low Power Electronics and Design (ISLPED)
From: Pai Chou <phchou@uci.edu>
Call for Papers: JETC Special Issue on Reliability and Device Degradation in Emerging Technologies
From: Fadi H Gebara <fhgebara@us.ibm.com>
Call for Papers: International Workshop on Logic & Synthesis (IWLS)
From: Stephen A. Edwards <sedwards@cs.columbia.edu>
Call for Participation: International Symposium on Physical Design (ISPD)
From: Azadeh Davoodi <adavoodi@wisc.edu>
Call for Participation: Ph.D. Forum at DAC
From: Laleh Behjat <laleh@ucalgary.ca>
Call for Papers: International Conference on Very Large Scale Integration (VLSI-SOC)
From: Matthew Guthaus <mrg@ucsc.edu>
Call for Papers: ACM Student Research Competition (SRC) at Design Automation Conference
From: Srinivas Katkoori <katkoori@cse.usf.edu>
Call for Papers: IEEE Annual Symposium on VLSI Design (ISVLSI)
From: Ankur Srivastava <ankurs@umd.edu>

Comments from the Editors

Dear ACM/SIGDA members,

In accordance with ACM Bylaw 6, the following SIGs will hold elections
in 2012: SIGACCESS, SIGACT, SIGCHI, SIGDA, ACM SIGGRAPH, SIGITE,
SIGPLAN, SIGSIM and SIGSOFT.

ACM Policy and Procedures require that those SIGs holding elections
notify their membership of candidates for elected offices. To see the
slate of candidates, please visit the 2012 ACM SIG Election site,
http://www.acm.org/sigs/elections.

In accordance with the SIG Bylaws, additional candidates may be placed
on the ballot by petition. All candidates must be Professional Members
of ACM, as well as members of the SIG. Anyone interested in
petitioning must inform ACM Headquarters (Pat Ryan, ACM, 2 Penn Plaza,
Suite 701, NY, NY 10121; ryan_p@acm.org) and the SIG Viability Advisor
(Barbara Boucher Owens, owensb@acm.org) of their intent to petition by
March 15.

Additional information will appear in the February or March issue of
ACM MemberNet and on the 2012 ACM SIG Election site.

Matthew Guthaus, E-Newsletter Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Sudeep Pasricha, E-Newsletter Associate Editor;
Srinivas Katkoori, E-Newsletter Associate Editor

Back to Contents

SIGDA News
"Automating the MEMS design processes"
http://www.eetimes.com/electronics-news/4235440/Automating-the-MEMS-design-proce...
With the market for micro-electro-mechanical system (MEMS) chips
growing at a 50 percent annual growth rate, according to Goldman Sachs
(New York), electronic design automation (EDA) tool vendor Coventor
Inc. (Cary, N.C.) aims to speed-up the MEMS chip design process by
adding scripted automation and by dramatically expanding the size of
the devices it can simulate.

"Microsoft keynoter to DesignCon attendees: 'Believe!'"
http://www.eetimes.com/electronics-news/4235287/Microsoft-keynoter-to-DesignCon-...
Microsoft's Ilan Spillinger will kick off day two of DesignCon with an
exciting keynote address that challenges the audience to harness the
power to "believe" as the basis of their design work. The keynote on
Tuesday, January 31 from noon to 12:30 will focus on the innovation of
Xbox through Kinect, drawing on his own personal experiences and his
own formula for fostering an environment of creativity.

"Researchers find bilayer graphene acts as insulator"
http://www.eetimes.com/electronics-news/4235176/Researchers-find-bilayer-graphen...
Research physicists at the University of California, Riverside have
identified an insulating property of “bilayer graphene” (BLG) formed
when two graphene sheets are stacked in a special manner.

"Researchers cool semi membrane by laser interaction"
http://www.eetimes.com/electronics-news/4235034/Researchers-cool-semi-membrane-b...
Researchers at the Niels Bohr Institute, University of Copenhagen,
have discovered a new method for laser cooling semiconductor
membranes--by heating the membrane.

"ST creates home network of self-powered nodes"
http://www.eetimes.com/electronics-news/4234870/ST-creates-smart-home-network-of...
STMicroelectronics NV has developed a platform for smart buildings
called GreenNet that includes self-powered wireless sensor nodes that
can be used to monitor a variety of parameters including temperature
and movement. In addition, ST (Geneva, Switzerland) is encouraging a
market in software to run on GreenNet networks by opening a dedicated
app store.

"10 unmistakable trends at CES 2012"
http://www.eetimes.com/electronics-news/4234615/10-unmistakable-trends-at-CES-20...
We roamed the show floor; and here are 10 unmistakable trends we think
will be appearing near you in the consumer electronics world in 2012.

"Do-It-Yourself EDA Flows Take Off in 2012"
http://www10.edacafe.com/nbc/articles/1/1050690/Do-It-Yourself-EDA-Flows-Take-Of...
When Verific started providing (System)Verilog and VHDL parsers in
2001, EDA companies were quick to jump on the bandwagon. Semiconductor
companies with internal CAD teams and FPGA companies supporting
customer design tools followed suit when they realized that they would
be better off re-using Verific's parsers than build their own.

"EDA Consortium Reports Revenue Increase for Q3 2011"
http://www10.edacafe.com/nbc/articles/1/1047897/EDA-Consortium-Reports-Revenue-I...
The EDA Consortium (EDAC) Market Statistics Service (MSS) today
announced that the Electronic Design Automation (EDA) industry revenue
increased 18.1 percent for Q3 2011 to $1543.9 million, compared to
$1307.0 million in Q3 2010. Sequential EDA revenue for Q3 2011
increased 7.4 percent compared to Q2 2011, while the four-quarters
moving average, which compares the most recent four quarters to the
prior four quarters, increased by 17.8 percent.

"Memristor 'brouhaha' bubbles under"
http://www.edn.com/article/520585-Memristor_brouhaha_bubbles_under.php
Blaise Mouttet, of Arlington, Virginia, has published a theoretical
paper on arXiv.org entitled "Memresistors and non-memristive
zero-crossing hysteresis curves" that seeks to demonstrate that there
are multiple dynamic systems which fall outside the constraints of the
so-called memristor, two-terminal memory device and yet produce
zero-crossing hysteresis curves.

"Geo-location tagging in smartphones to potentially cause major security risks"
http://www.edn.com/article/520457-Geo_location_tagging_in_smartphones_to_potenti...
Geo_location_tagging_in_smartphones_to_potentially_cause_major_security_risks.php
Commenting on the ICO's call for a rethink on location privacy,
Cryptzone says that geo-location tagging security issues are likely to
be a major issue in 2012—and that many users of smartphones are
unaware of the potentially serious security consequences of their use
of the technology.

Back to Contents

What is Wireless On-Chip Interconnect?
Ankit More and Baris Taskin
http://vlsi.ece.drexel.edu
Drexel University

Wireless on-chip interconnects are a radio-frequency (RF) alternative
to metal interconnects for global communication on an IC. RF
interconnect channels are based on:

1. On-chip micro-strip transmission lines [1],
2. On-chip antennas [2],
3. On-chip inductors based inductive coupling [3],
4. On-chip capacitors based capacitive coupling [4].

The micro-strip lines are used as guided-wave RF interconnects (RF-I[1])
on a layer for lateral communication whereas the other three are
configured as wireless RF interconnects used for lateral or vertical
communication.

The wireless interconnects are not envisioned to antiquate the metal
based interconnects but rather to be implemented in conjunction to
provide hybrid communication structures and networks-on-chip (NoC),
particularly for 2D or 3D multi-processor system-on-chips (MPSoCs).
The design of the wireless RF interconnects for all systems in general
but for multi-core systems in particular requires considerations
across a vast variety of subjects including, electro-magnetic theory,
network theory, wireless communication, VLSI design and design
automation. The multi-faceted design considerations are categorized
according to three primary design paradigms [5]:

P-1) Information Networking Paradigm: The information networking
paradigm considers higher level hybrid architectural design variables:
(a) the architecture of the hybrid NoC using the wireless interconnects,
(b) the number of wireless nodes and the arbitration protocol,
(c) the placement of the wireless nodes in a given network topology
constrained to the maximum possible communication distance,
(d) the protocol to select the wireless short-cut path over the wired
path.

It is proposed in [6], for instance, that the entire network be broken
up into subnets of computational cores with top-level hubs connected
with wireless ports for the high speed links conforming to a
small-world topology. Protocols for a collision free and quality of
service (QoS)-aware hybrid wireless NoCs, in presence of multiple
antennas at the same carrier frequency, are presented in [7].

P-2) Physical Implementation Paradigm: The physical implementation
paradigm considers both the antenna design and the transceiver
design. The antenna and the transceiver design depend on:
(a) the carrier frequency and the required bandwidth,
(b) the maximum communication distance,
(c) the maximum power dissipation,
(d) the output power of the transmitter and sensitivity of the
receiver,
(e) the electro-magnetic compatibility (EMC) and the electro-magnetic
interference (EMI) of the wireless system with the other on-chip
elements.

A silicon implementation of a wireless interconnects system at 15GHz
is presented in [2]. Dynamic reconfiguration of the wireless links
between multiple frequencies is proposed in [8]. Design guidelines
for reducing the impact of on-chip metal structures
(i.e. interconnects and vias) on the performance and characteristics
of the on-chip antennas are provided in [9].

P-3) Wireless Communication Paradigm: The wireless communication
paradigm models the communication channel. It provides the model for
the path loss between the antenna pair and the signal to noise ratio
(SNR) requirement based on the required bit-error-rate (BER) from the
wireless communication channel. The SNR places constraints on:
(a) the maximum wirelessly communicable distance,
(b) the required output power from the transmitter,
(c) the required sensitivity of the receiver.
These constraints in turn determine the power requirements of the
transceiver. The SNR requirement can be eased by utilizing
error-correction coding (ECC).

The wireless interconnect channel is modeled and characterized for the
path loss and delay spread in [10] and the BER and SNR for the
wireless interconnect system are analyzed in [11] and [12],
respectively.

In summary, the design of the hybrid NoC architectures using wireless
on-chip interconnects can potentially provide high throughput and
energy savings in 2D and 3D MPSoCs. However, their adaptability and
benefits depend on the integration of the multiple facets involved in
the design of such complex systems.

References

[1] M. F. Chang, V. P. Roychowdhury, L. Zhang, H. Shin and Y. Qian,
"RF/Wireless Interconnect for Inter- and Intra-chip Communications,"
Proceedings of the IEEE, vol. 89, pp. 456-466, April 2001.

[2] B. A. Floyd, C.-M. Hung and K.K. O, "Intra-chip Wireless
Interconnect for Clock Distribution Implemented with Integrated
Antennas, Receivers and Transmitters," IEEE Journal of Solid-State
Circuits, vol. 37, pp. 543-551, May 2002.

[3] N. Miura et al., "A 0.14pJ/b inductive-coupling transceiver with
digitally-controlled precise pulse shaping," IEEE Journal of
Solid-State Circuits, pp. 285-291, January 2008.

[4] A. Fazzi et al., "3D capacitive interconnections with mono- and
bi- directional capabilities," IEEE Journal of Solid-State Circuits,
pp. 275-284, January 2008.

[5] A. More and B. Taskin, "A Unified Design Methodology for a Hybrid
Wireless 2-D NoC," IEEE International Symposium on Circuits and
Systems (ISCAS), 2012.

[6] S. Deb, A. Ganguly, K. Chang, P. Pande, B. Beizer, and D. Heo,
"Enhancing Performance of Network-on-chip Architectures with
Millimeter-wave Wireless Interconnects," IEEE International Conference
on Application-specific Systems Architectures and Processors (ASAP),
2010, pp. 73-80.

[7] D. Zhao and Y. Wang, "SD-MAC: Design and Synthesis of a Hardware-
Efficient Collision-free QoS-aware MAC Protocol for Wireless
Network-on- chip," IEEE Transactions on Computers, vol. 57,
pp. 1230-1245, 2008.

[8] A. More and B. Taskin, "EM and Circuit Co-simulation of a
Reconfigurable Hybrid Wireless NoC on 2D ICs," IEEE International
Conference on Computer Design (ICCD), 2011, pp. 19-24.

[9] A. B. M. H. Rashid et al., "Interference Suppression of Wireless
Interconnection in Si Integrated Antenna," IEEE International
Interconnect Technology Conference (IITC), 2002, pp. 173-175.

[10] M. Sun, Y. P. Zhang, G. X. Zheng, and W. Y. Yin, "Performance of
intra-chip wireless interconnect using on-chip antennas and UWB
radios," IEEE Transactions on Antennas and Propagation, vol. 57,
pp. 2756-2762, September 2009.

[11] Y. P. Zhang, "Bit-error-rate Performance of Intra-chip Wireless
Interconnect Systems," IEEE Communications Letters, vol. 8, pp. 39-41,
January 2004.

[12] D. Bravo et al., "Estimation of the Signal-to-noise Ratio for
On-chip Wireless Clock Signal Distribution," IEEE International
Interconnect Technology Conference (IITC), 2000, pp. 9-11.

Back to Contents

Paper Submission Deadlines

VLSI Design Journal
(Special Issue in "New Algorithmic Techniques for EDA Problems”)
Publication date: Jun 22, 2012
Deadline: Feb 3, 2012
http://www.hindawi.com/journals/vlsi/si/eda/

ISLPED'12 - Int'l Symposium on Low Power Electronics and Design
Redondo Beach, CA
July 30-Aug 1, 2012
Deadline: March 2, 2012
http://www.islped.org

SLIP'12 - System Level Interconnect Prediction
(co-located with DAC'12)
San Francisco, CA
June 3, 2012
Deadline: Mar 5, 2012 (Abstracts due: Feb 27, 2012)
http://www.sliponline.org

MEMOCODE'12 - Int'l Conference on Formal Methods and Models for Codesign
Arlington, VA
Jul 16-18, 2012
Deadline: Mar 9, 2012 (Abstracts due: Mar 2, 2012)
http://www.memocode-conference.com

IWLS'12 - Int'l Workshop on Logic & Synthesis
Berkeley, CA
June 1-3, 2012
Deadline: Mar 9, 2012 (abstract); Mar 16, 2012 (paper)
http://www.iwls.org

ISVLSI'12 - IEEE Annual Symposium on VLSI Design
Amherst, MA
Aug 19-21, 2012
Deadline: Mar 9, 2012
http://www.eng.ucy.ac.cy/theocharides/isvlsi12/index.htm

PACT'12 - Int'l Conference on Parallel Architectures and Compilation
Techniques
Minneapolis, MN
Sep 21-25, 2012
Deadline: Mar 25, 2012
http://www.pactconf.org

BodyNets'12 - Int'l Conference on Body Area Networks
Oslo, Norway
Sep 24-26, 2012
Deadline: Apr 1, 2012
http://www.bodynets.org

IWBDA'12 - Int'l Workshop on Bio-Design Automation
San Francisco, CA (Co-located with DAC'12)
Jun 4-5, 2012
Deadline: Apr 2, 2012
http://iwbda2012.csb.pitt.edu

ASQED'12 - Asia Symposium on Quality Electronic Design
Kuala Lumpur, Malaysia
Jul 10-12, 2012
Deadline: Apr 4, 2012
http://www.asqed.org/

VLSI-SoC'12 - Int'l Conference on Very Large Scale Integration and System on Chip
Santa Cruz, CA
Oct 7-12, 2012
Deadline: Apr 9, 2012
http://vlsisoc2012.soe.ucsc.edu/

DFM&Y'12 - Int'l Workshop on Design for Manufacturability & Yield
San Francisco, CA (Co-located with DAC'12)
Jun 4, 2012
Deadline: Apr 2012 (tentative)
http://vlsicad.ucsd.edu/DFMY

ICCAD'12 - Int'l Conference on Computer-Aided Design
San Jose, CA (tentative)
Nov 2011 (exact dates to be announced)
Deadline: Apr 16, 2012
http://www.iccad.com

RTCSA'12 - Int'l Conference on Embedded and Real-Time Computing Systems and Applications
Seoul, Korea
Aug 20-22, 2012
Deadline: April 16, 2012
http://rtcsa.konkuk.ac.kr/

Wireless Health'12
San Diego, CA
Oct 22-25, 2012
Deadline: Apr 20, 2012
http://www.wirelesshealth2012.org/

Back to Contents

Upcoming Conferences and Symposia

ASP-DAC'12 - Asia and South Pacific Design Automation Conference
Sydney, Australia
Jan 30 - Feb 2, 2012
http://www.cse.unsw.edu.au/~babaks/aspdac/

ISSCC'12 - Int'l Solid-State Circuits Conference
San Francisco, CA
Feb 19-23, 2012
http://isscc.org/

DATE'12 - Design Automation and Test in Europe
Dresden, Germany
Mar 12-16, 2012
http://www.date-conference.com/

ISQED'12 - Int'l Symposium on Quality Electronic Design
Santa Clara, CA
Mar 19-21, 2012
http://www.isqed.org/

SPL'12 - Southern Conference on Programmable Logic
Bento Goncalves, Brazil
Mar 21-23, 2012
http://www.splconf.org/

ISPD'12 - Int'l Symposium on Physical Design
Napa, CA
Mar 25-28, 2012
http://www.ispd.cc

ASYNC'12 - Int'l Symposium on Asynchronous Circuits and Systems
(co-located with NOCS'12)
Copenhagen, Denmark
May 7-9, 2012
http://asyncsymposium.org

NOCS'12 - Int'l Symposium on Networks-on-Chip
(co-located with ASYNC'12)
Copenhagen, Denmark
May 9-11, 2012
http://www2.imm.dtu.dk/projects/nocs_2012/nocs/Home.html

EWME'12 - European Workshop on Microelectronics Education
Grenoble, France
May 9-11, 2012
http://cmp.imag.fr/conferences/ewme2012

BSN'12 - Int'l Conference on Wearable and Implantable Body Sensor Networks
London, UK
May 10-12, 2012
http://www.bsn2012.org

ISCAS'12 - Int'l Symposium on Circuits and Systems
COEX, Seoul, Korea
May 20-23, 2012
http://iscas2012.org/

IWLS'12 - Int'l Workshop on Logic & Synthesis
Berkeley, CA
June 1-3, 2012
http://www.iwls.org

DAC'12 - Design Automation Conference
San Fransisco, CA
Jun 3-7, 2012
http://www2.dac.com/

IWBDA'12 - Int'l Workshop on Bio-Design Automation
San Francisco, CA (Co-located with DAC'12)
Jun 4-5, 2012
http://iwbda2012.csb.pitt.edu

ISCA'11 - Int'l Symposium Computer Architecture
Portland, OR
Jun 9-13, 2012
http://isca2012.ittc.ku.edu/

AHS'12 - NASA/ESA Conference on Adaptive Hardware and Systems
Nuremburg, Germany
Jun 25-28, 2012
http://www.see.ed.ac.uk/ahs2012/

Back to Contents

Upcoming Funding Opportunities

ASEE

Office of Naval Research (ONR) Sabbatical Leave Program
Deadline: N/A
http://onr.asee.org/

Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Deadline: Continuous
http://www.asee.org/fellowships/nrl/about.cfm

DARPA

Microsystems Technology Office-Wide Broad Agency - DARPA-BAA-10-35
Deadline: September 1, 2012
https://www.fbo.gov/spg/ODA/DARPA/CMO/DARPA-BAA-10-35/listing.html

DOD

Robust Computational Intelligence - AFOSR-BAA-2011-01
Deadline: Continuous
http://www.grants.gov/search/search.do?oppId=88213&mode=VIEW

Systems and Software - AFOSR-BAA-2011-01
Deadline: Continuous
http://www.grants.gov/search/search.do?oppId=88213&mode=VIEW

ERDC BAA - Computational Science and Engineering (ITL-1)
Deadline: Continuous
http://www.mvk.usace.army.mil/contract/docs/BAA.pdf

Advanced Distributed Sensor Technologies - BAA 57-09-06
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm

Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm

High Performance Computing on Massively Parallel Architectures (BAA 64-09-01)
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm

ASEE-NRL Postdoctoral Fellowship Program
Deadline: N/A
http://hroffice.nrl.navy.mil/jobs/postdoc.htm

DOE

Postdoctoral Appointments
Deadline: N/A
http://www.sandia.gov/careers/postdoc.html

Sabbaticals and Faculty Appointments
Deadline: continuous
http://www.nrel.gov/rpp/sabbaticals.html

McDonnell Foundation

Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Deadline: continuous
http://www.jsmf.org/programs/cs/

NSF

Cyberlearning: Transforming Education (Cyberlearning)
Deadline: February 15, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf11587

Secure and Trustworthy Cyberspace (SaTC)
Deadline: February 22, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf12503

Industry/University Cooperative Research Centers Program (I/UCRC)
Deadline: March 6, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf12516

Expeditions in Computing
Deadline: March 10, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf10564

Cyber-Physical Systems (CPS)
Deadline: March 15, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf12520

Back to Contents

Call for Papers: VLSI Design Journal Special Issue on New Algorithmic Techniques for EDA Problems

CALL FOR PAPERS
VLSI Design Journal Call for Papers (deadline Feb. 3, 2012):
Special Issue on New Algorithmic Techniques for EDA Problems

Please see http://www.hindawi.com/journals/vlsi/si/eda/ for details.
The details are also given below.

Original papers are invited for a special issue of the VLSI Design
journal on "New Algorithmic Techniques in EDA". There are two broad
sets of effects that result from the rapidly decreasing feature sizes
in CMOS VLSI (ASICs, SoCs and microprocessor designs). (a) Significant
increase in the number and the diversity of systems that are
implemented on a single chip (b) Further exacerbation of old problems
and the introduction of new ones such as electrical/physical effects
like power dissipation and leakage/temperature issues at all levels,
lithography and manufacturing problems leading to appreciable
variability, and reliability of the design stemming from reduced
feature sizes, to name a few. These issues present significant
challenges to the entire range of EDA tools from ESL (e.g., memory
synthesis and hierarchy design, effective power analysis and
optimization) to gate-level synthesis (e.g., detailed power
optimization across millions of gates under timing yield and
voltage-island constraints). EDA software has thus become immensely
complex, and algorithmic innovations are needed to tackle these new
problems with efficiency and efficacy at various stages of the VLSI
design flow (e.g., ESL including high-level synthesis, logic/physical
synthesis, physical extraction and timing models,
variability/manufacturing aware optimization, simulation and analysis,
and verification).

TOPICS

We are thus asking for original paper submissions addressing critical
problems in EDA using effective algorithmic techniques that are either
new or uncommon in EDA. More formally put, the desired algorithmic
techniques are those that either (a) are completely new in their usage
in the EDA domain, or (b) have been proposed only over the last five
years or so or (c) have been proposed more than five years back, but
have been used sparsely in EDA. Potential algorithmic approaches
include, but are not limited to:

** Various polynomial time approximation schemes (e.g., PTAS, EPTAS, FPTAS)
** Randomized algorithms
** Discretized network flow (DNF)
** Multilevel techniques for scalability
** Parallel processing (especially for multicore CPU/GPU processors)
including concurrent data structures
** Metaheuristics, for example, tabu search, greedy randomized adaptive
search procedures (grasp), ant colony optimization, multistart methods,
and constraint satisfaction
** Machine learning and statistical techniques
** Data mining techniques

The proposed algorithms should empirically demonstrate efficacy in
solving the targeted EDA problems. When submitting your paper to this
special issue, please include a new section titled "New Algorithmic
Technique(s) Used" that immediately follows the "Introduction"
section, for an explicit identification of the algorithmic
technique(s) used, and a justification, possibly with citations, that
they fit into one of the above categories (a-c). Also, as with any
other journal publication, if the submission is an extension to a
conference paper, please also include a paragraph of justification in
the "Introduction" section (at least 30% new material is required).

SUBMISSIONS

Before submission authors should carefully read over the journal's Author
Guidelines, which are located at

http://www.hindawi.com/journals/vlsi/guidelines/

Prospective authors should submit an electronic copy of their complete
manuscript through the journal Manuscript Tracking System at

http://mts.hindawi.com/

according to the following timetable:

IMPORTANT DATES

Manuscript Due Friday, 3 February 2012
First Round of Reviews Friday, 27 April 2012
Publication Date Friday, 22 June 2012

FURTHER INFORMATION

Lead Guest Editor:
Shantanu Dutt, dutt@uic.edu, Department of ECE,
University of Illinois at Chicago, Chicago, IL, USA
Guest Editors:
Dinesh Mehta, dmehta@mines.edu, Department of EECS,
Colorado School of Mines, Golden, Co, USA
Gi-Joon Nam, gnam@us.ibm.com, IBM Research Labs, Austin, TX, USA

Back to Contents

Call for Papers: TCAD Special Section on Three-dimensional Integrated Circuits and Microarchitectures

CALL FOR PAPERS: IEEE Transactions on CAD
Special Section on Three-dimensional Integrated Circuits and Microarchitectures

In recent years, the area of three-dimensional (3D) Integrated
Circuits has become a very attractive research topic due to its
potential for extending MooreÕs momentum in the next decade. The key
benefits of 3D ICs over traditional two-dimensional chips include the
potential of reduced overheads for global interconnects, higher
packing densities and smaller footprints, heterogeneous integration,
and faster times-to-market. To efficiently exploit the benefits of 3D
technologies, design techniques and methodologies for supporting 3D
designs are imperative; design space exploration at the architectural
level is also essential to fully take advantage of the 3D integration
technologies to build a high- performance, energy-efficient integrated
systems, GPUs, system-on-chips, heterogeneous systems, and other
integrated systems.

We are pleased to announce a call for papers for a special section of
TCAD on Three-dimensional (3D) Integrated Circuits. We welcome
submissions to this special section based on new, unpublished
contributions. Submissions may also be based on work previously
published in refereed conferences/workshops; if so, the submission
must contain at least 30% new materials, and the authors must provide
a cover letter clearly stating how the submission differs from and/or
expands on the previously-published work.

Areas of interest for this special section include (but are not limited to) the
following topics:

* Physical design methodologies/tools/algorithms for 3D
* High-level synthesis/logic synthesis for 3D ICs
* ESL design methodologies and tools for 3D ICs
* Thermal analysis and thermal-aware designs
* 3D architectures and design space exploration
* 3D Test, design-for-test, and debug techniques
* Signal and power integrity, and ESD in 3D
* Chip-package co-design for 3D
* Economic benefit/cost trade-off studies
* Application, product, or test-chip case studies

Please submit your paper at the TCAD website,

http://mc.manuscriptcentral.com/tcad

Please specify "Special Section on 3D ICs and Microarchitectures" on
your cover page and in the notes section of the Web site submission
form.

IMPORTANT DATES

Submission Deadline: 15 March 2012
Acceptance Notice: 1 July 2012
Final Manuscript Due: 1 August 2012

GUEST EDITORS

Yuan Xie, Pennsylvania State University, yuanxie@cse.psu.edu
Gabriel H. Loh, AMD Research. Gabe.loh@amd.com

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Call for Papers: International Conference on Formal Methods and Models for Codesign (MEMOCODE)

ACM/IEEE Tenth International Conference on Formal Methods and Models for Codesign

MEMOCODE 2012

http://www.memocode-conference.com

Arlington, Virginia
July 16-18, 2012

The goal of MEMOCODE 2012, the tenth in a series of successful
international conferences, is to gather researchers and practitioners
in the field of the design of modern hardware and software system to
explore ways in which future design methods can benefit from new
results on formal methods.

IMPORTANT DATES

Abstract submission deadline: March 2, 2012
Paper submission deadline: March 9, 2012
Notification of acceptance: May 4, 2012
Final Version for Papers: May 18, 2012

Hardware-software systems face increasing design complexity including
tighter constraints on timing, power, costs, and reliability. MEMOCODE
seeks submissions that present novel formal methods and design
techniques addressing these issues to create, refine, and verify
hardware/software systems. We also invite application-oriented papers,
and especially encourage submissions that highlight the design
perspective of formal methods and models, including success stories
and demonstrations of hardware/software codesign. Furthermore, we
invite poster presentations describing ongoing work with promising
preliminary results.

Topics of interest for regular submissions include but are not limited
to

* system- and transaction-level modeling and verification, abstraction
and refinement between different modeling levels, formal,
semi-formal, and specification-driven verification,

* design and verification methods for composition of concurrent
systems: multi-core platform architectures, systems-on-chip,
networks-on-chip,

* formal methods and tools for hardware and software verification
including theorem proving, decision procedures,

* non-traditional and domain-specific design languages for hardware
and software, novel models of computation, and new design paradigms
that unify hardware and software design,

* system-level estimation of performance and power in heterogeneous
hardware/software architectures,

* applications and demonstrators of formal design methodologies and
case studies of innovative system-level design flows,

* modeling and reuse of intellectual property at system-level, and

* design abstraction and high-level design demonstrating productivity
and quality in generating and validating RTL and software.

PROCEEDINGS

Conference proceedings will be published by the IEEE Computer Society.

SUBMISSION

Submissions of research and experience papers will only be accepted
through the conference website. Papers must not exceed 10 pages and
must be formatted following IEEE Computer Society guidelines.
Submissions must be written in English, describe original work, and
not substantially overlap papers that have been published or are being
submitted to a journal or another conference with published
proceedings. Poster submissions should consist of an abstract of at
most 250 words. The abstract will be distributed to the conference
attendants but will not be published. Note that the poster deadline is
different from the paper deadline.

SUBMISSION WEBSITE

http://www.easychair.org/conferences/?conf=memocode2012

DESIGN COMPETITION

MEMOCODE will again have a design contest. The contest will start
March 1, 2012. The deadline for submission is 31 March 2012 and the
notification of the results is on May 13, 2012. The conference will
sponsor at least two prize categories, each with a significant cash
award. In past editions we awarded a $1000 prize in each of the two
categories. Each team that submits a complete and working entry will
be invited to submit for review a 2-page abstract for the formal
conference proceedings and present a poster at the conference; winning
teams will be invited to contribute a 4-page short paper and present
their work at the conference. Each team submitting a completed and
working entry will also receive a commemorative plaque with their name
and results. Please refer to the website for more information and
updates.

SPONSORS

IEEE CEDA, IEEE CAS, ACM SIGBED, and ACM SIGDA.

ORGANISATION COMMITTEE

General Chair
Sandeep Shukla (Virginia Tech)

Program Chairs
Luca Carloni (Columbia)
Daniel Kroening (Oxford)

Design Contest Chair
Stephen Edwards (Columbia)

Finance Chair
James Hoe (CMU)

Publication Chair
Jens Brandt (TU Kaiserslautern)

PROGRAM COMMITTEE

Roderick Bloem (Graz)
Luca Carloni (Columbia)
Abhijit Davare (Intel)
Robert de Simone (INRIA)
Stephen A. Edwards (Columbia)
Franco Fummi (Verona)
Thierry Gautier (INRIA)
Alain Girault (INRIA)
David Greaves (Cambridge)
Daniel Grosse (Bremen)
Connie Heitmeyer (NRL)
Franjo Ivancic (NEC Labs)
Barbara Jobstmann (CNRS)
Michael Kishinevsky (Intel)
Christoph Kirsch (Salzburg)
Daniel Kroening (Oxford)
Luciano Lavagno (Torino)
Elizabeth Leonard (NRL)
John O'Leary (Intel)
Philip Ruemmer (Uppsala)
Klaus Schneider (Kaiserslautern)
Satnam Singh (Google)
Jean-Pierre Talpin (INRIA)
Michael Theobald (D. E. Shaw)
Shobha Vasudevan (UIUC)
Thomas Wahl (Northeastern)
Fei Xie (Portland)
Qi Zhu (UC Riverside)

STEERING COMMITTEE

Arvind (MIT)
Masahiro Fujita (University Tokyo)
Rajesh Gupta (UC San Diego)
Connie Heitmeyer (NRL)
James Hoe (CMU)
Sandeep Shukla (Virginia Tech)
Jean-Pierre Talpin (INRIA)

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Call for Papers: International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

CALL FOR PAPERS

RTCSA 2012
The 18th IEEE International Conference on Embedded and Real-Time
Computing Systems and Applications

http://rtcsa.konkuk.ac.kr/

August 20 - 22, 2012
Seoul, Korea

SUBMISSION DEADLINE: Apr 16, 2012, 12:00 (noon) GMT+9

Embedded software has become a necessity in almost every aspect of the
daily lives of individuals and organizations, from self-contained
applications to those embedded in various devices and services (mobile
phones, vital sign sensors, medication dispensers, home appliances,
engine ignition systems, etc). A large proportion of these systems
are mission/life critical and performance sensitive.

The 18th IEEE International Conference on Embedded and Real-Time
Computing Systems and Applications (RTCSA 2012) will bring together
researchers and developers from academia and industry for advancing
the technology of embedded and real-time systems, and ubiquitous
computing applications. The conference has the following goals: to
investigate advances in embedded and real-time systems and ubiquitous
computing applications; to promote interaction among the areas of
embedded computing, real-time computing and ubiquitous computing; to
evaluate the maturity and directions of embedded and real-time system
and ubiquitous computing technology. RTCSA 2012 invites submissions
of papers presenting a high quality original research and development
for the conference tracks: (1) Embedded Systems, (2) Real-time
Systems, and (3) Ubiquitous Computing/Cyber-physical Systems.

SCOPES: Following the tradition of RTCSA, the conference has three
tracks: embedded systems, real-time systems, and ubiquitous computing.
The topics of interest include, but are not limited to:

EMBEDDED SYSTEMS TRACK:
- System level design and HW/SW co-design
- Embedded system design practices
- Operating systems and scheduling
- Software and compiler issues for heterogeneous multi-core embedded
platform
- Embedded system architecture
- Networks-on-chip design
- Power/thermal-aware design issues
- Memory issues for multi-core embedded platform
- Hardware and software techniques for fault tolerance
- Reconfigurable computing architecture and software support

REAL-TIME SYSTEMS TRACK:
- Real-time operating systems
- Real-time scheduling
- Timing analysis
- Databases
- Programming languages and run-time systems
- Middleware systems
- Design and analysis tools
- Communication networks and protocols
- Case studies and applications
- Media processing and transmissions
- Real-time aspects of Wireless sensor networks
- Energy aware real-time methods

UBIQUITOUS COMPUTING/CYBER-PHYSICAL SYSTEMS TRACK:

- Real-time issues in ubiquitous computing and cyber-physical systems
- Tools, infrastructures and architectures for ubiquitous computing
and cyber-physical systems
- Devices and enabling technologies for ubiquitous computing and
cyber-physical systems
- Design and verification methodologies for cyber-physical systems
- Applications of wireless sensor networks
- Ubiquitous computing applications
- Cyber-physical systems applications
- User interfaces and interaction design issues for ubiquitous computing
- Privacy and security issues and implications of ubiquitous computing
- Location-dependent and context-aware computing
- Evaluation methods for ubiquitous computing devices, systems, and
applications

Regular Paper Submission:

The submitted manuscript must describe original work not previously
published and not concurrently submitted elsewhere. Submissions
should be no more than 10 pages in IEEE conference proceedings format
(two-column, single-space, 10pt). The prospective authors should
submit their papers on RTCSA 2012 paper submission site:
http://www.rtcsa.org (in preparation for now)

Work-in-Progress Session:

This session provides an opportunity for researchers attending RTCSA
to present and discuss their research. This one hour event will
feature concurrent short presentations by all participants organized
in poster formats. More detailed information is available on the web.

IMPORTANT DATES:

Paper Submission: Apr 16, 2012, 12:00 (noon) GMT+9
Acceptance Notification: May 23, 2012
Camera Ready Submission: June 3, 2012

WIP Abstract Submission: June 18, 2012
WIP Notification: June 22, 2012
WIP Camerca Ready Submission: July 13, 2012

Early Registration Deadline: June 24, 2012

ORGANIZING COMMITTEE:

Steering Committee:
Tatsuo Nakajima, Waseda University, Japan (Chair)
Tei-Wei Kuo, National Taiwan University, Taiwan
Joseph K. Ng, Hong Kong Baptist University, China
Hide Tokuda, Keio University, Japan
Seongsoo Hong, Seoul National University, Korea
Sang H. Son, University of Virginia, USA

General Co-Chairs:
Yunheung Paek, Seoul National University, Korea
Jorgen Hansson, Chalmers University, Sweden

Program Co-Chairs:
Real-Time Systems: Steve Goddard, University of Nebraska-Lincoln, USA
Ubiquitous Comp/Cyber-Physical Systems: Chin-Fu Kuo, National University
of Kaohsiung, Taiwan
Embedded Systems: Jongeun Lee, UNIST, Korea

WIP Chair:
Chang-gun Lee, Seoul National University, Korea
Shinpei Kato, UC Santa Cruz, USA

Financial Chair:
Hyeonsang Eom, Seoul National University, Korea

Local Arrangement Chair:
Sung-Soo Lim, Kookmin University, Korea

Publication Chair:
Jangwoo Kim, Postech, Korea

Web Chair:
Neungsoo Park, Kunkuk University, Korea

Publicity Co-Chairs:
Thomas Nolte, Malardalen University, Sweden (Europe)
Yoshinori Takeuchi, Osaka University, Japan (Asia)
Sudeep Pasricha, Colorado State University, USA (USA)

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Call for Papers: International Symposium on Low Power Electronics and Design (ISLPED)

CALL FOR PAPERS - ISLPED 2012 (http://www.islped.org)

IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN

Location: Redondo Beach, CA, USA
Date: July 30-August 1, 2012

****IMPORTANT DATES****

Technical paper submission deadline: March 2, 2012
Notification of paper acceptance: April 20, 2012
Camera-ready version due: May 20, 2012

Electronics advances especially in mobile applications require
significant reductions in power, and this is a critical area for the
design of electronic circuits and systems. The International
Symposium on Low Power Electronics and Design (ISLPED) is the premier
forum for presentation of recent advances in all aspects of low power
design and technologies, ranging from process and circuit
technologies, simulation and synthesis tools, to system level design
and optimization.

Specific topics include, but are not limited to, the following two main
areas, each with three sub-areas:

1. Architecture, Circuits, and Technology
1.1. Technologies and Digital Circuits
1.2. Logic and Microarchitecture Design
1.3. Analog, MEMS, Mixed Signal and Imaging Electronics

2. Design Tools, System and Software Design
2.1. CAD & Design Tools
2.2. System Design and Methodologies
2.3. Software Design and Optimization

The scope of the Symposium includes innovative techniques in the following
areas:
- Process Technologies and new devices for ultra-low power systems
- Digital circuit techniques in deeply scaled technologies
- Clock generation and distribution to enable reduced power
- Ultra-low power memory circuits, including novel non-volatile memories
- Power circuits, linear and switching regulators and voltage references
- Enabling technologies for >100x power reduction in "More than Moore"
- Logic and microarchitecture design for reduction of power
- Optimization of power and performance at microarchitecture and system levels
- Analog and mixed signal circuits such as data converters and amplifiers
- Design Tools, System, and Software Design for ultra-low power optimization.
- Tools and methodologies that enable orders of magnitude power reduction
- Complex SOC systems that show significant reduction in power.
- Power minimization techniques for analog and digital circuits, including
novel energy harvesting, battery management and renewable energy topics.
- Battery technologies and energy generation and management for ultra-low
power systems, including wireless sensor nodes, low-power display systems,
actuators, imaging, and motor drives.
- Techniques for digitally-assisted analog and analog-assisted digital that
show significant power reduction over more traditional techniques.

****TECHNICAL PAPER SUBMISSIONS****

Submissions should be full-length papers of up to 6 pages
(double-column format, font size 9pt to 10pt), including all
illustrations, tables, references and an abstract of no more than 100
words. Papers exceeding the six-page limit will not be reviewed.
Submission must be anonymous: papers identifying the authors will be
automatically rejected.

Electronic submission in pdf format only via the web is required.
More information on electronic submission to ISLPED'12 can be found at
http://www.islped.org/.

ORGANIZING COMMITTEE:

General Co-Chairs
-Massimo Poncino, Politecnico di Torino
-Naresh Shanbhag, UIUC

TPC Co-Chairs
-Pai Chou, UC Irvine
-Ajith Amerasekara, Texas Instruments

Local Arrangement Chair
-Puneet Gupta, UCLA

Treasurer
-Yuan Xie, Penn State Univ.

Publicity Co-Chairs
-Luca Benini, Università di Bologna
-John Donovan (Low Power Design)

Design Contest Chair
-Chia-Lin Yang, National Taiwan Univ.

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Call for Papers: JETC Special Issue on Reliability and Device Degradation in Emerging Technologies

Call for Papers
JETC Special Issue on Reliability and Device Degradation in Emerging Technologies

In recent years, reliability has emerged as a critical metric for
semiconductor technologies. Temporal changes in device and system
performance due to physical and environmental effects are resulting in
larger design margins, increased test costs and increased number of
in-field failures. In order to understand these problems, and
potential solutions, we are pleased to announce a call for papers for
a special issue of the ACM Journal on Emerging Technologies in
Computing Systems on reliability and device degradation in emerging
technologies

This special issue will focus on the reliability, aging and robustness
of devices, circuits and systems in emerging technologies. Of
particular interest is innovations with nanotechnology and
non-traditional Si CMOS.

Topics of interest include, but are not limited to:

Device reliability and degradation modeling and simulation New aging
and reliability phenomena associated with new device structures Design
methodologies for improved reliability Memory cell and sub system
reliability Reconfigurable systems reliability New devices
sensitivities to SER and upset events CAD tools and simulation engines
aimed at reliability

Information about JETC, including instructions for manuscript
preparation, is available at http://jetc.acm.org. Please submit your
manuscript electronically at http://mc.manuscriptcentral.com/jetc, and
indicate “Special Issue on “Reliability and Device Degradation in
Emerging Technologies” on the cover page and in the notes section of
the submission form. Manuscripts must conform to the JETC style
(double-spaced in 10-point font), and be limited to 20 pages for
research papers, and 40-50 pages for tutorial and survey papers.
Expanded versions of previously published conference research papers
are welcome as long as they contain at least 30% new material; authors
should clearly state in a footnote on the first page how the
manuscript differs from the conference paper. Papers simultaneously
submitted elsewhere may be returned without review. Longer papers can
be considered upon request and at the discretion of the
Editor-in-Chief.

Important Dates:

Submission Deadline: March 15, 2012
Author Notification: June 1, 2012
Revised Manuscripts Due: July 1, 2012
Notice of Final Acceptance: August 1, 2012
Final Manuscripts Due: September 15, 2012
Publication Date: January 2013

GUEST EDITORS:

Dr. Rahul M. Rao
Watson Research Center
IBM Research
raorahul@us.ibm.com

Dr. Fadi H. Gebara
Austin Research Lab
IBM Research
fhgebara@us.ibm.com

Back to Contents

Call for Papers: International Workshop on Logic & Synthesis (IWLS)

Call for Papers
The 21th International Workshop on Logic & Synthesis
sponsored by the ACM/SIGDA and by the IEEE
June 1 - 3, 2012
University of California, Berkeley
Co-located with the Design Automation Conference
website: http://www.iwls.org

The International Workshop on Logic and Synthesis is the premier
forum for research in synthesis, optimization, and verification
of integrated circuits and systems. Research on logic synthesis
for emerging technologies and for novel computing platforms, such
as nanoscale systems and biological systems, is also strongly
encouraged. The emphasis is on novelty and intellectual rigor.
The workshop encourages early dissemination of ideas and results.
The workshop accepts complete papers as well as abstracts,
highlighting important new problems in the early stages of
development, without providing complete solutions.

Topics of interest include (but are not limited to): synthesis
and optimization; power and timing analysis; testing, validation
and verification; architectures and compilation; and design
experiences. Submissions on modeling, analysis and synthesis for
emerging technologies and platforms are particularly encouraged.

Both complete papers as well as extended abstracts highlighting
new problems and new topics of research are welcomed. Only
original and previously unpublished material is permitted.
Submissions must be no longer than 8 pages, double column,
10-point font. Accepted papers are distributed only to IWLS
participants.

The workshop format includes paper presentations, posters, invited
talks, social lunch and dinner gatherings, and recreational
activities. Submissions are made electronically through the EDAS
system. Please see the website for instructions: http://www.iwls.org

Abstract submission: March 9, 2012
Submission deadline for papers: March 16, 2012 - 11.59pm HAST
Notification of acceptance: April 2, 2012
Final version due: May 5, 2012

************************************************************
*** The submission deadline of March 16, 2012 is final, ****
**** there will be no extension. ****
************************************************************

For questions, contact: Ilya Wagner (email: ilya.wagner@intel.com)

We are striving offer heavily discounted registration rates for
students and unemployed attendees. In addition, attendees who plan to
attend both IWLS and DAC will have higher priority for the several
travel support opportunities provided through DAC.

General Chair:
Ilya Wagner, Intel

Program Chair:
Philip Brisk, University of California, Riverside

Special Sessions Chair:
Andrea Pellegrini, University of Michigan

Local Arrangements Chair:
Alan Mishchenko, University of California, Berkeley

Special Activities Chair:
Tobias Welp, University of California, Berkeley

Executive Committee:
Valeria Bertacco, University of Michigan
Igor Markov, University of Michigan

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Call for Participation: International Symposium on Physical Design (ISPD)

Call for Participation

ACM International Symposium on Physical Design 2012
With a tribute to Prof. C.-L. Liu
http://www.ispd.cc

Location: Napa California, USA
Sponsored by ACM SIGDA with Technical Co-sponsorship from IEEE CAS

The International Symposium on Physical Design (ISPD) provides a
premier forum to exchange ideas and promote research on critical areas
related to the physical design of VLSI systems. ISPD-2012 will be held
March 25-28, 2012 in Napa, California.

The 2012 technical program is now available at
http://ispd.cc/ispd12_program.html. Registeration can be made from
the conference website. For information about travel and accomodation,
please also visit the conference website.

SYMPOSIUM ORGANIZATION

General Chair: Jiang Hu (Texas A&M Univ.) [jianghu@ece.tamu.edu]
Steering Committee Chair: Yao-Wen Chang (National Taiwan Univ.) [ywchang@cc.ee.ntu.edu.tw]
Technical Program Chair: Cheng-Kok Koh (Purdue Univ.) [chengkok@purdue.edu]
Publications Chair: Cliff Sze (IBM) [csze@us.ibm.com]
Publicity Chair/Webmaster: Azadeh Davoodi (Univ. Wisconsin) [adavoodi@wisc.edu]

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Call for Participation: Ph.D. Forum at DAC

Ph.D. Forum at DAC

Call for Participation

The Ph.D. Forum at the Design Automation Conference is a poster
session hosted by SIGDA for Ph.D. students to present and discuss
their dissertation research with people in the EDA community. It has
become one of the premier forums for Ph.D. students in design
automation to get feedback on their research and for industry to see
academic work in progress: 400 - 500 people attended the last
forums. Participation in the forum is competitive with acceptance rate
of around 30%. Limited funds will be available for travel assistance,
based on financial needs. The forum is open to all members of the
design automation community and is free-of-charge. It is co-located
with DAC, that is held in June 3-7, to attract the large DAC audience,
but DAC registration is not required in order to attend this event.

Contact Information

For questions not addressed on this page, please send e-mail
Dr. Shiyan Hu: shiyan@mtu.edu. Please include "DAC Ph.D. Forum" in the
subject line of your email.

Eligibility

* Students with at least one published or accepted conference,
symposium or journal paper.
* Students within 1-2 years of dissertation completion and students
who have completed their dissertation during the 2011-2012 academic
year.
* Dissertation topic must be relevant to the DAC community.
* Previous forum presenters are not eligible.
* Students who have presented previously at the DATE and ASP-DAC
Ph.D. forums are eligible, but will be less likely to receive travel
assistance.

Important Dates

* Submission Deadline: Monday, March 15, 2012, 5:00PM MDT
* Notification Date: TBA

Submission Requirements

* A two-page PDF abstract of the dissertation (in two-column format,
using 10-11 pt. fonts and single-spaced lines), including name,
institution, advisor, contact information, estimated (or actual)
graduation date, whether the work has been presented at ASP-DAC
Ph.D. Forum or DATE Ph.D. Forum, as well as figures, and
bibliography (if applicable). The two-page limit on the abstract
will be strictly enforced: any material beyond the second page will
be truncated before sending to the reviewers. Please include a
description of the supporting paper, including the publication
forum. A list of all papers authored or co-authored by the student,
related to the dissertation topic and included in the two-page
abstract, will strengthen the submission.
* A published (or accepted) paper, in support of the submitted
dissertation abstract. The paper must be related to the dissertation
topic and the publication forum must have a valid ISBN number. It
will be helpful, but is not required, to include your name and the
publication forum on the first page of the paper. Papers on topics
unrelated to the dissertation abstract or not yet accepted will not
be considered during the review process. Please Note:
* The abstract is the key part of your submission. Write the abstract
for someone familiar with your technical area, but entirely
unfamiliar with your work. Clearly indicate the motivation of your
Ph.D. dissertation topic, the uniqueness of your approach, as well
as the potential impact your approach may have on the topic.
* In the beginning of the abstract, please indicate to which track
your submission belongs.
* Proper spelling, grammar, and coherent organization are critical:
remember that the two pages may be the only information about
yourself and your PhD research available to the reviewers.
* All submissions must be made electronically through EasyChair
system.
* Please include the supporting paper with the abstract in one PDF
file and submit the single file. There are many free utilities
available online which can merge multiple PDF files into a single
file if necessary.

Tracks

1. System-level Design, Synthesis and Optimization (including
network-on-chip, system-on-chip and multi/many-core, HW/SW
co-design, embedded software issues, modeling and simulation
2. High Level Synthesis, Logic Level Synthesis
3. Physical Design and Manufacturability
4. Power and Reliability Analysis and Optimization (including power
management from system level to circuit level, thermal management,
process variability management)
5. Timing Analysis, Circuit and Interconnect Simulation
6. Signal Integrity and Design Reliability, Analog/Mixed Signals and RF
7. Verification, Testing, Pre- and Post-Silicon Validation, Failure
Analysis
8. Reconfigurable and Adaptive Systems
9. Emerging Design and Technologies (carbon nano-tubes, molecular
electronics, MEMS, micro-fluidic system, biologically-inspired
systems, quantum computing, etc.)

Submissions dealing with power modeling, analysis, and/or optimization
may be submitted to any track, depending on the abstraction level and
contents of the work. Same principle also applies to variability-aware
and fault-tolerant design and analysis. Please consult your advisor to
determine which track is the best fit for your submission. If you
still have questions about the most appropriate submission track, you
are encouraged to contact the TPC Chair, Dr. Gayatri Mehta
(Gayatri.Mehta@unt.edu).

Contact Information

For questions not addressed on this page, please send e-mail
Dr. Shiyan Hu: shiyan@mtu.edu. Please include "DAC Ph.D. Forum" in the
subject line of your email.

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Call for Papers: International Conference on Very Large Scale Integration (VLSI-SOC)

20th IFIP/IEEE International Conference on Very Large Scale Integration
VLSI-SoC 2012
October 7-10, 2012
Santa Cruz, CA, USA
Dream Inn Hotel

http://www.vlsi-soc.com

VLSI-SoC 2012 is the 20th in a series of international conferences
sponsored by IFIP TC 10 Working Group 10.5, IEEE CEDA and IEEE CASS
that explores the state-of-the-art and the new developments in the
field of Very Large Scale Integration (VLSI) and System-on-Chip
(SoC). Previous Conferences have taken place in Edinburgh, Trondheim,
Tokyo, Vancouver, Munich, Grenoble, Gramado, Lisbon, Montpellier,
Darmstadt, Perth, Nice, Atlanta, Rhodes, Florianopolis, Madrid and
Hong Kong. The purpose of VLSI-SoC is to provide a forum to exchange
ideas, and show academia/industrial research results in the fields of
VLSI/ULSI Systems, SoC design, VLSI CAD and Microelectronic Design and
Test.

Topics of interest include but are not limited to:
* Analog and Mixed-Signal IC Design
* Circuits and Systems for Micro-sensing Applications
* 3-D Integration, Physical Design, Compact Modeling, and
Electromagnetic Analysis
* Design for Variability, Reliability, Fault Tolerance, Test
* Digital Signal Processing and Image Processing IC Design
* New Devices, MEMS and Microsystems
* Prototyping, Validation, Verification, Modeling and Simulation
* System-On-Chip Design, Digital Architectures
* Embedded Systems Design and Real-Time Systems
* Reconfigurable Systems, Compiler
* Logic and High-Level Synthesis
* Low-Power and Thermal-aware Design

PAPER SUBMISSION

Papers should present original research results not published or
submitted for publication in other forums. Electronic submission in
PDF format to the http://www.vlsi-soc.com web site is required. The
proceedings will be published by IEEE and available through IEEE
Xplore. They will be distributed during the conference to all
participants. A selection of the conference best papers will be
invited to submit an extended version to be included as chapters of a
book to be published by Springer.

Paper Submission Deadline: April 9, 2012
Special Session Proposal: April 9, 2012
Notification of acceptance: June 17, 2012
Camera-ready: July 11, 2012

PAPER FORMAT

Papers should not exceed 6 pages (single-spaced, 2 columns, 10pt
font).Submissions should be in camera-ready, following the IEEE
proceedings specifications located at:
http://www.ieee.org/web/publications/pubservices/confpub/AuthorTools/conferenceT...

PAPER PUBLICATION AND PRESENTER REGISTRATION

Papers will be accepted for regular or poster presentation at the
conference. Every accepted paper MUST have at least one author
registered to the conference by the time the camera-ready paper is
submitted; the author is also expected to attend the conference and
present the paper. A limited number of travel grants are available to
needy PhD students. Please see the web site for more information.

PHD FORUM

The VLSI-SoC 2012's Ph.D. Forum is a poster session dedicated to the
exchange of ideas and experiences of Ph.D. students from different
parts of the world. Elected Ph.D. students have an opportunity to
discuss their thesis and research work with specialists within the
system and design automation communities. This exchange offers a good
opportunity for students to receive valuable feedback and gain
exposure in the job market. Furthermore, this forum also provides a
great chance for industry officials to meet junior researchers, giving
an avenue for incorporating the latest research developments into
their companies. More information in the conference web page.

ORGANIZING COMMITTEE:

General Chair:
Matthew Guthaus, UC Santa Cruz, USA

Program Chairs:
Ayse Coskun, Boston Univ., USA;
Andreas Burg, EPFL, Switzerland

Special Sessions Chair:
Sung-Mo "Steve" Kang, UC Santa Cruz, USA
Jose Renau, UC Santa Cruz, USA

Local Arrangement Chair:
Jose Renau, UC Santa Cruz, USA

Publication Chairs:
Srinivas Katkoori, Univ of South Florida, USA;
Ricardo Reis, UFRGS, Brazil

Publicity Chair:
Ricardo Reis, UFRGS, Brazil

Registration Chair:
Rajsaktish Sankaranarayanan, UC Santa Cruz, USA

Finance Chair:
Baris Taskin, Drexel, USA

PhD Forum Chair:
Ken Pedrotti, UC Santa Cruz, USA

Steering Committee:
Manfred Glesner, TU Darmstadt, Germany;
Salvador Mir, TIMA, France;
Ricardo Reis, UFRGS, Brazil;
Michel Robert, U. Montpellier, France;
Luis Miguel Silveira, INESC ID, Portugal

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SIGDA E-News 1 February 2012, Vol. 42, No. 02