Search
Connect
Upcoming
Navigation
SIGDA E-News 1 December 2012, Vol. 42, No. 12
1 December 2012, Vol. 42, No. 12
Online archive: http://www.sigda.org/newsletter
- SIGDA News
From: Lin Yuan <yuanl@synopsys.com>
From: Sudeep Pasricha <sudeep@colostate.edu> - What is Assertion Based Verification?
Contributing author(s):
Shobha Vasudevan <shobhav@illinois.edu>, Univ. of Illinois at Urbana-Champaign
From: Srinivas Katkoori <katkoori@cse.usf.edu> - Paper Submission Deadlines
From: Sudeep Pasricha <sudeep@colostate.edu> - Upcoming Conferences and Symposia
From: Sudeep Pasricha <sudeep@colostate.edu> - Upcoming Funding Opportunities
From: Prabhat Mishra <prabhat@cise.ufl.edu> - Call for Papers: GLSVLSI 2013
From: Alex K. Jones <akjones@pitt.edu> - Call for Papers: NOCS 2013
From: Carole-Jean Wu <carole-jean.wu@asu.edu> - Call for Papers: MSE 2013
From: Laleh Behjat <laleh@ucalgary.ca> - Call for Papers: ViPES 2013
From: Brian F. Veale <veale@acm.org>
Comments from the Editors
Dear ACM/SIGDA members,
In this issue, we have a very interesting article on Assertion
based Verification. If you are interested in contributing to this column in
the future, please contact Srinivas Katkoori <katkoori@cse.usf.edu> or Sudeep
Pasricha <sudeep@colostate.edu>. An article only needs to be about 1 page long
with several references. All articles are included in the ACM digital library
and there is no restriction for the reproduction of the article for printed
publication later.
Sudeep Pasricha, E-Newsletter Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Prabhat Mishra, E-Newsletter Associate Editor
Srinivas Katkoori, E-Newsletter Associate Editor
SIGDA News
"Globalfoundries' FinFET wafers set to roll"
http://www.eetimes.com/electronics-news/4402427/Globalfoundries-FinFET-MPW
The first multiproject wafer runs for customers testing Globalfoundries' 14-nm
FinFET manufacturing process technology could start as soon as the first
quarter of 2013, according to Mike Noonen, executive vice president of worldwide
marketing and sales at the foundry chip maker.
"IBM flash interconnect aims to bust bottlenecks"
http://www.eetimes.com/electronics-news/4402238/IBM-flash-interconnect-aims-to-b...
IBM is developing a new storage I/O technology geared for flash in the wake of
its acquisition of Texas Memory Systems. Big Blue is expected to court an
ecosystem of third parties to support the technology which may take the form of
a value-added layer on top of an existing interconnect standard.
"Flexible electronics breakthrough claimed"
http://www.eetimes.com/electronics-news/4402180/Flexible-electronics-breakthroug...
Researchers from the University of Pennsylvania have demonstrated the
ability to coat nanoscale particles of the semiconducting material cadmium selenide
on flexible plastics, a breakthrough that could lead to high-performance electronics
on flexible substrates.
"Why the ARM architecture is shaped the way it is"
http://www.eetimes.com/electronics-news/4401986/Why-the-ARM-architecture-is-shap...
It is arguable that ARM and Intel, the two companies locked in head-to-head
processor competition, represent two different poles and philosophies.
"Mars Curiosity gets down to science"
http://www.eetimes.com/electronics-news/4401890/Mars-Curiosity-gets-down-to-scie...
Since its dramatic touch down on Aug. 6, the Mars Science Laboratory –better
known as “Curiosity” – has been checked out by its operators at the
Jet Propulsion Laboratory before embarking on an unprecedented two-year exploration
of Gale Crater in search of signs of past microbial life on Mars.
"London Calling: Intel's 14-nm process delay"
http://www.eetimes.com/electronics-news/4401725/London-Calling--Intel-process-de...
The good news for Intel's Irish contingent is that they get to go home early.
The bad news is that they get to go home early due to a reported project delay.
"Apple A6X uncovered"
http://www.eetimes.com/electronics-news/4401455/Apple-A6X-uncovered
Inside the new Apple iPad—or iPad 4—lies a modified A6 processor dubbed the
A6X. This modified A6 processor still features two application processor cores
and operates at 1 GHz. However, the architecture has been modified to include
quad-core graphics as opposed to the three-core graphics of the original A6.
"Huawei, Altera mix FPGA, memory in 2.5-D device"
http://www.eetimes.com/electronics-news/4401446/Huawei--Altera-mix-FPGA--memory-...
Huawei will package an FPGA and a Wide I/O memory on a 2.5-D silicon
interposer to bust through memory bandwidth limits in communications systems.
The technology presents thorny challenges but could become critical in
networking, said a senior scientist for Huawei.
"Bill Gates: From DOS to PC domination"
http://www.eetimes.com/electronics-news/4401352/Bill-Gates--From-DOS-to-PC-domin...
A Harvard drop out with penchant for programming and a whole lot of chutzpah
turned out to be one of the most influential leaders of the microcomputer era.
In the course of helping define the software industry, Bill Gates won himself
a place as one of the most influential people in electronics.
"Steve Jobs: Guru of the user experience"
http://www.eetimes.com/electronics-news/4400935/Steve-Jobs--Guru-of-computing-to...
The founder of Apple popularized a gospel of surprising and delighting users
with designs that were simple, yet elegant and above all easy to use. Along
the way, he helped drive the shift to digital media. Jobs also cut an example
of tenacity and the independence to, in the words of his own slogan, “think
different.”
"EE Times 40th: 10 electronics visionaries to watch"
http://www.eetimes.com/electronics-news/4400587/Visionaries-changing-the-world-i...
Predicting the future is always fraught with peril, but the visionaries
featured here are boldly going where no one has gone before.
"Researchers spot materials challenges for future chips"
http://www.eetimes.com/electronics-news/4400703/Research-uncovers-materials-chal...
A team of physicists at McGill University have demonstrated that electrical
current may be drastically reduced when wires from two dissimilar metals meet,
calling attention to a future technology hurdle for semiconductor design.
"New FPGA-Based Prototyping Solution Delivers Up To 3x System Performance
Improvement"
http://www10.edacafe.com/nbc/articles/1/1136625/New-FPGA-Based-Prototyping-Solut...
Synopsys' HAPS-70 Series' Scalable Architecture and Integrated
Hardware/Software Prototyping Flow Accelerate Throughput While Increasing
Prototyping Capacity to 144 Million ASIC Gates
"Beyond "Printed" Electronics"
http://www10.edacafe.com/nbc/articles/1/1136341/Beyond-Printed-Electronics
The rush for Printed Electronics is on. High speed & high volume makes it
an economical solution for many areas of manufacturing that are beginning
to incorporate "smarts or functions" for everyday products.
What is Assertion Based Verification?
Shobha Vasudevan
ECE Dept., University of Illinois at Urbana-Champaign
Design verification is universally accepted to be a "pain point" of the
modern system design cycle. We build systems that we do not know how to
verify. Then, we spend a lot of human and computing resources as well as
time trying to convince ourselves that what we built is correct. At the
heart of the verification process is the to "know what one is looking for,"
or the specifications of how the system should behave. The verification
itself is only as good as the specifications or properties that you check
for. Assertions provide a mechanism to express desirable or required
invariant properties that should be true in the system.
Assertion-based verification has emerged as an important candidate solution
in contemporary verification industry [7][8]. In a recent survey [10],
it was reported that assertion usage in the hardware design industry
has increased from 37% to 69% between 2007 and 2010. It is slated for
further increase, as EDA tools and products are supporting the assertion
environment. Assertions can be checked dynamically during simulation of
the design using directed/random stimulus, or they can be formally verified
to be true for all reachable states of the design. Either way, they are
a cornerstone of Register Transfer Level (RTL) verification.
Assertions are expressed in Boolean and temporal logic. They can express
properties like "if a request line is high, the request will be granted
within 5 cycles" or "it is always possible to transition to a reset state
from any other state of the machine" or "concurrent requests in an arbiter
are prioritized according to an order." The expressed properties can be
safety (something bad never happens) or liveness (something good always
happens). Although the expressive power of most assertions is Linear
Temporal Logic (LTL), modern assertion based verification tool environments
support different assertion specification languages. Property Specification
Language (PSL) and System Verilog Assertions (SVA) are very popular choices
of assertion specification languages.
Assertion Generation
The key question then is: How are these assertions generated? Assertion
generation is an entirely manual effort in the hardware system design
cycle [7]. Placing too many assertions can result in an unreasonable
performance overhead. Placing too few assertions, on the other hand, results
in insufficient coverage of behavior. The trade-off point for crafting minimal,
but effective (high coverage) assertions takes multiple iterations and
person-months to achieve. Another challenge with assertion generation is
due to the modular nature of system development. A module developer would
write local assertions that pertain to his/her module. Maintaining consistency
of inter-modular global assertions as the system evolves in this fragmented
framework is very tedious. In sequential hardware, temporal properties that
cut across time cycles are usually the source of subtle, but serious bugs.
It is difficult for the human mind to express and reason with temporal
relations, making temporal assertion generation very challenging. Anecdotally,
designers as a community are not enthusiastic about writing assertions,
since it is unfamiliar territory.
Over the past few years, some solutions for automatic assertion have spawned.
Among the commercial assertion generation tools, NextOp's BugScope,
Jasper's JasperGold are building products in this space. The first
published work to solve this problem is from the University of Illinois
at Urbana-Champaign, GoldMine (2009).
The GoldMine solution [1][5][6] is a creative way to solve this problem.
GoldMine combines statistical, dynamic methods (data mining) with static,
deterministic methods (source code static analysis and formal verification).
Static source code analysis of RTL is used to provide domain guidance to
the data miner. Data mining algorithms make inferences about the dynamic
behavioral data of the system, while formal verification is used to
check the truth/falsehood of the inferences. Such inferred assertions
can capture complex functional and temporal properties of the hardware,
which can surpass assertions generated by human reasoning.
GoldMine automates a ubiquitous but currently manual system design
process. This has a broad impact on utilization and channeling of
human and computing resources within the system's verification cycle.
The marriage of statistical and static analysis methods to infer
knowledge about a system is a meta-technique that can be used in
other domains where we need to analyze the systems that we build.
This "GoldMine principle" can be used in many contexts such as
software testing, software security and post-Silicon validation.
At present, GoldMine uses seven different specialized data mining
algorithms along with complex RTL static analysis technology. The
standard problem faced by mechanical output is verbosity and lack
of readability. GoldMine includes set-covering and equivalence
partitioning algorithms to address this problem. It also has the
ability to output assertions at the word level, for enhanced
readability. The word level assertion generation is done by using
efficient RTL weakest precondition computation [4].
Assertion Evaluation
Among assertions that are manually or automatically generated, how
can we tell which assertions are "better" than the others? Higher
coverage could be a metric, but assertion coverage is not well
defined at the RT-level. Other desirable features of an assertion
include readability, closeness to specification, unexpectedness
and exposure to corner case scenarios. Coming up with a figure of
merit to incorporate all these subjective metrics is a challenge.
GoldMine has a methodology for ranking assertions according to a
figure of merit that we have defined and found empirically to be
valuable.
The attempt of automatic techniques is typically to mimic the human
generated result. For eg., consider logic synthesis algorithms that
automate the process of custom gate-level design. Interestingly,
for assertion generation, the human generated result is not the gold
standard! This is because property generation is elusive to the human
being. In the initial stages of GoldMine, we tried to get subjective
designer rankings for the generated assertions. We ranked assertions
between 1-4, where 1 stands for too trivial, 2 stands for not
interesting, but essential, 3 for subtle design intent and 4 for
"I don't get it!." Surprisingly, there were rank 4 assertions that
were many logic levels deep that the designers found too complex to
write on their own. Hence, subjective metrics are enlightening but
not useful for evaluation. This is why an objective "goodness metric"
is required for assertions.
Coverage of an Assertion
Coverage achieved during verification is the single most important
parameter in determining the quality of verification results. In
conventional simulation based verification, coverage of a set of tests
or a test suite is measured using various metrics such as code coverage,
toggle coverage, and FSM coverage. Code coverage measures the fraction of
statements in the design source executed while simulating the test
suite. Since code coverage can be easily related to the source code
and reporting it adds little overhead to simulation, it is the most
popular coverage metric. In the context of formal verification, the
fraction of states in the state transition graph of a design covered
by an assertion is typically used as a coverage metric [9]. This is
hard to compute, due to the size of the state transition graph that
needs to be built and traversed. Although code coverage is an important
coverage metric for verification, no such metric for assertions is
widely used by standard verification tools. GoldMine addresses this
problem by defining and computing code coverage metrics for an assertion [2].
Depending on whether the assertion is used in formal or simulation
based verification, the definition of coverage of an assertion needs
to be adapted. Since the simulation process is inherently not exhaustive,
we base the definition of coverage of an assertion on the coverage
of a test that cause the antecedent of the assertion to evaluate to
true (simulation based coverage). In the formal verification context,
we expand the definition to span all possible paths in the design and
focus on the statements that affect the correctness of that assertion
(correctness based coverage).
Using RTL Assertions Beyond Static and Dynamic Checking
Random stimulus is applied late in the validation phase, when the design
and assertion-based verification environment are mature enough to
withstand and interpret random behavior. On a recent visit to a leading
microprocessor company, I was told that the random pattern generation
phase is like witchcraft! No one knows when to stop, so they stop at
an arbitrary number- 3 million cycles of simulation!
Since GoldMine can be generated from random stimulus as data, it explores
the random stimulus space and distills it into assertions that a human
can review. GoldMine’s data mining, then, gains knowledge about design
spaces that are as yet unexplored by a human-directed validation phase.
Eventually, the manual, iterative process of validation will arrive at
a point of high coverage. Using GoldMine, however, this step can be done
very early in the design, making a leap in the validation cycle. If an
unintended invariant behavior is observed, a bug is detected. Otherwise,
an assertion that can be used for all future versions of the design has
been generated. GoldMine assertions can therefore be used to calibrate
the directed test suite, where a metric of goodness for the tests can
be to stimulate a majority of the assertions.
Assertions from Specifications
This is the holy grail of verification! Assertions generated manually
in RTL should not simply check if the given RTL design is correct, but
they should check if the given RTL design implements the design intent,
or specification. For eg., if a pipelined implementation of an adder
implements the pipelining signals correctly, but does not handle overflow
as specified, the assertion based verification should reveal this. Hence,
ideally, the assertions should be derived from the specification, whether
it is manual or automatic generation of assertions. However, in reality,
there is no such thing as a standard specification. Models of desired
behavior range from English documents to UML diagrams, executable formal
specification languages, micro-architecture level simulators, C/C++
emulation models, etc. In the absence of a detailed specification,
assertions and properties are derived only locally at RTL. We have
attempted to generate assertions at transaction level using SystemC
TLM models [3]. However, at this level, the model is built less for
accurate functionality, and more for performance evaluation. Hence the
true specification that is detailed enough to derive useful information
and yet more abstract than the implementation is still elusive.
GoldMine can be downloaded for research purposes from
goldmine.csl.illinois.edu.
References
[1] S. Vasudevan, D. Sheridan, D. Tcheng, S. Patel, W. Tuohy, and
D. Johnson, “GoldMine: Automatic assertion generation using data mining
and static analysis,” in Proc. of the Conf. on Design, automation and
test in Europe, 2010.
[2] V. Athavale, “Coverage analysis for assertions and emulation based
verification,” Master’s thesis, University of Illinois at Urbana-Champaign,
2012.
[3] L. Liu, D. Sheridan, V. Athavale, and S. Vasudevan, “Automatic
generation of assertions from system level design using data mining,”
in 9th IEEE/ACM Conf. on Formal Methods and Models for Codesign
(MEMOCODE), 2011.
[4] L. Liu, C. Lin, and S. Vasudevan, “Word level feature discovery to
enhance the quality of assertion mining,” in IEEE/ACM Intl. Conf. on
Computer Aided Design, 2012.
[5] L. Liu, D. Sheridan, W. Tuohy, and S. Vasudevan, "A Technique
for Test Coverage Closure Using GoldMine", in IEEE Trans. on CAD of
Integrated Circuits and Systems vol. 31, no. 5, pp. 790-803, 2012.
[6] L. Liu, D. Sheridan, W. Tuohy, and S. Vasudevan, "Towards
coverage closure: Using GoldMine assertions for generating design
validation stimulus," in Proc. of the Conf. on Design, automation
and test in Europe, 2011.
[7] H. Foster, D. Lacey, and A. Krolnik, Assertion-Based Design.
Norwell, MA, USA: Kluwer Academic Publishers, 2003
[8] A. Gupta, “Assertion-based verification turns the corner,” IEEE
Design and Test, vol. 19, no. 4, pp. 131–132, 2002.
[9] H. Chockler, O. Kupferman, R. P. Kurshan, and M. Y. Vardi,
"A practical approach to coverage in model checking," in Proc. of
Computer Aided Verification, 2001.
[10] Mentor Graphics Blogs
http://blogs.mentor.com/verificationhorizons/blog/author/hfoster/
DAC'13 – Design Automation Conference
Austin, TX
Deadline: Dec 3, 2012 (Abstracts due: Nov 27, 2012)
User track deadline: Feb 6, 2013
Jun 2-6, 2013
http://www.dac.com/
NOCS'13 – Int’l Symposium on Networks-on-Chip
Tempe, AZ
Deadline: Dec 7, 2012 (Abstracts due: Dec 4, 2012)
Apr 21-24, 2013
http://chatha.faculty.asu.edu/nocs2013/
HOST'13 – International Symposium on Hardware-Oriented Security and Trust
Austin, TX
Deadline: Dec 10, 2012
June 2-3, 2013
http://www.hostsymposium.org/
ASYNC'13 – Int’l Symposium on Asynchronous Circuits and Systems
Santa Monica, CA
Deadline: Dec 14, 2012 (Abstracts due: Dec 7, 2012)
May 19-22, 2013
http://asyncsymposium.org
TAU'13 – Int’l Workshop on Timing Issues in the Specification and
Synthesis of Digital Systems
(co-located with ISPD’13)
Stateline, NV
Deadline: Dec 18, 2012
Mar 27-29, 2013
http://www.tauworkshop.com/
MSE'13 - Microelectronics Systems Education
Austin, TX
Deadline: Jan 15, 2013
Jun 2-3, 2013
http://www.mseconference.org
Upcoming Conferences and Symposia
MICRO'12 - Int'l Symposium on Microarchitecture
Vancouver, Canada
Dec 1-5, 2012
http://www.microarch.org/micro45/
ICFPT'12 - Int'l Conference on Field-Programmable Technology
Seoul, Korea
Dec 10-12, 2012
http://www.icfpt.org/
ICPADS'12 - Int'l Conference on Parallel and Distributed Systems
Singapore, Singapore
Dec 17-19, 2012
http://pdcc.ntu.edu.sg/icpads2012/
HiPC'12 - Int'l Conference on High Performance Computing
Pune, India
Dec 18-21, 2012
http://www.hipc.org/
ISED’12 – Int’l Symposium on Electronic System Design
Kolkata, India
Dec 19-22, 2012
http://ised.seedsnet.org/
VLSI'13 - Int'l Conference on VLSI Design
Pune, India
Jan 5-10, 2013
http://www.vlsidesignconference.org/
HiPEAC'13: Int'l Conference on High Performance Embedded Architectures &
Compilers
Berlin, Germany
Jan 21-23, 2013
http://www.hipeac.net/ hipeac2013
ASP-DAC'13 - Asia and South Pacific Design Automation Conference
Yokohama, Japan
Jan 22-25, 2013
www.aspdac.com/aspdac2013/
ISSCC'13 - Int'l Solid-State Circuits Conference
San Francisco, CA
Feb 17-21, 2012
http://isscc.org/
ISQED'13 - Int'l Symposium on Quality Electronic Design
Santa Clara, CA
Mar 11-13, 2013
http://www.isqed.org/
DATE'13 - Design Automation and Test in Europe
Grenoble, France
Mar 18-22, 2013
http://www.date-conference.com/
ISPD’13 – Int’l Symposium on Physical Design
(co-located with TAU’13)
Lake Tahoe, CA
Mar 24-27, 2013
http://www.ispd.cc
ISCAS'13 - Int'l Symposium on Circuits and Systems
Beijing, China
May 19-23, 2013
http://iscas2013.org/
Upcoming Funding Opportunities
ASEE
Office of Naval Research (ONR) Summer Faculty Research Program
Deadline: December 05, 2012
http://onr.asee.org/
National Defense Science and Engineering Graduate (NDSEG) Fellowship Program
Deadline: December 16, 2012
http://ndseg.asee.org/
Office of Naval Research (ONR) Sabbatical Leave Program
Deadline: Continuous
http://onr.asee.org/
Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Deadline: Continuous
http://www.asee.org/fellowships/nrl/about.cfm
DARPA
Strategic Technology Office (STO) Broad Agency Announcement (BAA)
Deadline: January 12, 2013
http://www.darpa.mil/Opportunities/Solicitations/STO_Solicitations.aspx
Microsystems Technology Office-Wide Broad Agency Announcement
Deadline: September 1, 2014
http://www.grants.gov/search/search.do?oppId=197074&mode=VIEW
DOD
Postdoctoral Fellowship Award
Deadline: December 4, 2012
http://www.grants.gov/search/search.do?oppId=203153&mode=VIEW
Multidisciplinary University Research Initiative (MURI)
Deadline: December 10, 2012
http://www.grants.gov/search/search.do?mode=VIEW&oppId=56417
National Defense Science and Engineering Graduate Fellowship Program (NDSEG)
Deadline: December 14, 2012
http://ndseg.asee.org/application_instructions
Young Investigator Program (YIP)
Deadline: January 4, 2013
http://www.grants.gov/search/search.do?oppId=204213&mode=VIEW
Research Interests of the Air Force Office of Scientific Research
Deadline: Continuous
http://www.grants.gov/search/search.do?mode=VIEW&oppId=158973
High Performance Computing on Massively Parallel Architectures (BAA 64-09-01)
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm
DOE
Director's Postdoctoral Fellows
Deadline: Continuous
http://www.lanl.gov/science/postdocs/appointments.shtml
Postdoctoral Appointments
Deadline: N/A
http://www.sandia.gov/careers/postdoc.html
Sabbaticals and Faculty Appointments
Deadline: continuous
http://www.nrel.gov/rpp/sabbaticals.html
McDonnell Foundation
Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Deadline: continuous
http://www.jsmf.org/programs/cs/
NSF
Expeditions in Computing
Deadline: December 10, 2012
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=503169
Information and Intelligent Systems (IIS): Core Programs
Deadline: Dec 17 (small), 2012
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13707
Computer and Network Systems (CNS): Core Programs
Deadline: Dec 17 (small), 2012
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=12765
Computing and Communication Foundations (CCF): Core Programs
Deadline: Dec 17 (small), 2012
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=503220
Cyber-Enabled Sustainability Science and Engineering (CyberSEES)
Deadline: Dec 4, 2012 (LOI) / Feb 5, 2013
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=504829
National Robotics Initiative (NRI)
Deadline: December 11, 2012 (small) / January 23, 2013 (large)
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=503641
Cyber-Physical Systems (CPS)
Deadline: January 29, 2013
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=503286
Core Techniques and Technologies for Advancing Big Data Science & Engineering
(BIGDATA)
Deadline: June 13, 2013
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=504767
ONR
Young Investigator Program (YIP)
Deadline: Jan 4, 2013
http://www.grants.gov/search/search.do?oppId=204213&mode=VIEW
GLSVLSI 2013
Paris, France, May 2-4 2013
http://www.glsvlsi.org/
Sponsored by ACM SIGDA, with Technical Support of IEEE CEDA
The 23rd edition of GLSVLSI will be held in Paris, France and collocated with
the ACM European Computing Research Congress (ECRC), http://ecrc.acm.org.
Original, unpublished papers describing research in the general area of
VLSI are solicited. Both theoretical and experimental research results are
welcome. Proceedings will be published by the ACM and will be available through
the ACM Digital Library. For more information, visit http://www.glsvlsi.org/.
Program Tracks:
> VLSI Design: design of ASICs, microprocessors/micro-architectures, embedded
processors, analog/digital/mixed-signal systems, NoC, interconnects, memories,
and FPGAs.
> VLSI Circuits: analog/digital/mixed-signal circuits, RF and communication
circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits.
> Computer-Aided Design (CAD): hardware/software co-design, logic and
behavioral synthesis, logic mapping, simulation and formal verification,
layout (partitioning, placement, routing, floorplanning, compaction),
algorithms and complexity analysis
> Low Power and Power Aware Design: circuits, micro-architectural techniques,
thermal estimation and optimization, power estimation methodologies, and
CAD tools
> Testing, Reliability, Fault-Tolerance: digital/analog/mixed-signal testing,
design for testability and reliability, online testing techniques, static
and dynamic defect- and fault-recoverability, and variation-aware design
> Emerging Technologies: nano technology, molecular electronics, quantum
devices, biologically-inspired computing, CNT, SET, RTD, QCA, VLSI aspects
of sensor and sensor networks, and CAD tools for emerging technology devices
and circuits
> Post-CMOS VLSI: evolutionary computing, optical computing, quantum computing,
reversible logic, spin-based computing, biological computation, nanotechnology,
molecular electronics, quantum devices, biologically-inspired computing.
Emphasis should be on the analysis, novel circuits and architectures,
modeling, CAD tools, and design methodologies.
Paper submission deadline: December 15, 2012
Acceptance Notification: February 15, 2013
Camera-Ready Paper Due: March 1, 2013
Paper Submission: Authors are invited to submit full-length (6 pages maximum),
original, unpublished papers along with an abstract of at most 200 words.
To enable blind review, the author list should be omitted from the main
document. Previously published papers or papers currently under review for
other conferences/journals should not be submitted and will not be considered.
Electronic submission in PDF format to the http://www.glsvlsi.org website
is required. Author and contact information (name, street/mailing address,
telephone, fax, e-mail) must be entered during the submission process.
Paper Format: Submissions should be in camera-ready two-column format,
following the ACM proceedings specifications located at:
http://www.acm.org/sigs/pubs/proceed/template.html
and the classification system detailed at: http://www.acm.org/class/1998
Paper Publication and Presenter Registration: Papers will be accepted for
regular or poster presentation at the symposium. Every accepted paper
MUST have at least one author registered to the symposium by the time the
camera-ready paper is submitted; the author is also expected to attend the
symposium and present the paper.
General Chair
Jose L. Ayala - Complutense Univ. of Madrid, Spain
Program Chair
Alex K. Jones - University of Pittsburgh, USA
Patrick Madden - Binghamton University, USA
Proceedings Chair
Ayse Coskun - Boston University, USA
Website Chair
Theocharis Theocharides - University of Cyprus, Cyprus
Steering Committee
David Atienza - EPFL, Switzerland
Iris Bahar - Brown University, USA
Sanjukta Bhanja - University of South Florida, USA
Erik Brunvand - University of Utah, USA
Joseph Cavallaro - Rice University, USA
Fabrizio Lombardi - Northeastern University, USA
Enrico Macii - Politecnico di Torino, Italy
Ken Stevens - University of Utah, USA
Yuan Xie - Penn State University, USA
Tong Zhang - Rensselaer, USA
April 21-24, 2013
Tempe, Arizona, USA
The International Symposium on Networks-on-Chip (NOCS) is the premier event
dedicated to interdisciplinary research on on-chip and chip-scale communication
technology, architecture, design methods, applications and systems. NOCS brings
together scientists and engineers working on NoC innovations and applications
from inter-related research communities, including computer architecture,
networking, circuits and systems, embedded systems, and design automation.
Topics of interest include, but are not limited to:
NoC architecture and implementation
- Network architecture (topology, routing, arbitration)
- NoC Quality of Service
- Timing, synchronous/asynchronous communication
- NoC reliability issues
- Network interface issues
- NoC design methodologies and tools
- Signaling & circuit design for NoC links
- Physical design of interconnect & NoC
NoC analysis and verification
- Power, energy & thermal issues (at the NoC, un-core and/or system-level)
- Benchmarking & experience with real NoC-based hardware
- Modeling, simulation, and synthesis of NoCs
- Verification, debug & test of NoCs
- Metrics and benchmarks for NoCs
NoC application
- Mapping of applications onto NoCs
- NoC case studies, application-specific NoC design
- NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
- NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
- Network design for 2.5D & 3D stacked logic and memory
NoC at the un-core and system-level
- Design of memory subsystem (un-core) including memory controllers, caches,
cache coherence protocols & NoCs
- NoC support for memory and cache access
- OS support for NoCs
- Programming models including shared memory, message passing and novel
programming models
- Multi/many-core workload characterization & evaluation
- Optical, RF, & emerging technologies for on-chip/inpackage interconnects
- Issues related to large-scale systems (datacenters, supercomputers) with
NoC-based systems as building blocks
Electronic paper submission requires a full paper, up to 8 double-column IEEE
format pages, including figures and references. The program committee in a
double-blind review process will evaluate papers based on scientific merit,
innovation, relevance, and presentation. Submitted papers must describe
original work that has not been published before or is under review by another
conference at the same time. Each submission will be checked for any significant
similarity to previously published works or for simultaneous submission to other
archival venues, and such papers will be rejected. Furthermore, NOCS will
notify the technical chair of the venue where the duplicate was submitted.
Please see the paper submission instructions for details.
Proposals for tutorials, special sessions, and panels are also invited. Please
see the detailed submission instructions for paper, tutorial, special sessions,
and panel proposals at the submission page. A special section related to the
theme of the conference will be organized in one of the IEEE journals.
Abstract registration deadline
Nov 19, 2012
Full paper submission deadline
Nov 26, 2012
Proposals for tutorials, special sessions and panels Jan 11, 2013
Notification of acceptance
Feb 1, 2013
Final version due
Mar 1, 2013
Organizing Committee
General Co-Chairs:
Karam S. Chatha, Arizona State University, USA
Chita R. Das, Penn State University, USA
Finance Chair:
Sudeep Pasricha, Colorado State, USA
Registration Chair:
Mohammed Al Faruque, Siemens, USA
Publicity Chair:
Carole Jean Wu, Arizona State University, USA
Program Co-Chairs:
John Bainbridge, Sonics Inc., USA
Natalie Enright Jerger, University of Toronto, CA
Publications Chair:
Paul Gratz, Texas A&M, USA
Tutorials/Demo Chair
Zhonghai Lu, KTH, Sweden
Industrial Chair
Umit Ogras, Intel, USA
Contact Information
Karam Chatha, kchatha@asu.edu
John Bainbridge, jbainbridge@ieee.org
Chita Das, das@cse.psu.edu
Natalie Enright Jerger, enright@eecg.toronto.edu
Call for Papers: 9th IEEE International Conference on Microelectronic Systems
Education (MSE 2013)
----------------------------------------------------------------------
June 2 – 3, 2013, Austin, Texas
www.mseconference.org
CALL FOR PAPERS
The IEEE Computer Society International Conference on Microelectronic Systems
Education is the premier
conference dedicated to furthering undergraduate and graduate education in
designing and building innovative
microelectronics systems. The conference is held in the U.S. in odd years,
and in Europe in even years, when it is called the
European Workshop on Microelectronics Education (EWME). MSE is co-located
with the Design Automation Conference (DAC) providing the participants with a
unique opportunity to attend both conferences.
Topics of Interest
The MSE conference provides an excellent opportunity for educators and
industry to work together to ensure continued excellence in the field of
microelectronic systems. Of particular interest is incorporation of emerging
trends in the microelectronic system industry and research into the classroom.
Papers are invited in (but not limited to) the following areas:
- Pedagogical innovations using a wide range of technologies, including
nanometer-scale integrated circuits,
low-power design, nanotechnology, application-specific integrated circuits
(ASICs), field programmable gate
arrays (FPGAs), multicore/many-core processors, graphics processing units
(GPUs), sensor networks, and
embedded systems.
- Educational techniques including novel curricula and laboratories,
assessment methods, distance learning,
textbooks, and design projects.
- Industry and academic collaborative programs and teaching.
- Preparing students for industry, entrepreneurship, academics, and/or
research.
Submission
Papers submitted to MSE 2013 should not exceed four (4) pages in
length. Submissions must comply with IEEE Computer Society formatting
requirements. Submissions in PDF or postscript format may be submitted
on-line at www.mseconference.org. Submissions will be judged on
originality, appropriateness, technical strength, assessment,
and other relevant criteria.
Important Dates
Submission of papers: January 15, 2013
Notification of acceptance: March 15, 2013
Submission of final papers: April 8, 2013
General Chair
John Nestor
Lafayette College
nestorj@lafayette.edu
Program Chair
Matthew R. Guthaus
University of California, Santa Cruz
mrg@ucsc.edu
Call for Papers: Workshop on Virtual Prototyping of Parallel and Embedded
Systems (ViPES 2013)
------------------------------------------------------------------------
May 24th, Boston, USA (in conjunction with IPDPS)
www.vipes-workshop.org
1st Workshop on Virtual Prototyping of Parallel and Embedded Systems ViPES,
The 1st Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES
2013) will be held in Boston, USA in May 2013. ViPES 2013 is associated with
the 27th Annual International Parallel & Distributed Processing Symposium
(IPDPS 2013) and is sponsored by the IEEE Computer Society's Technical
Committee on Parallel Processing.
Virtual prototyping stands for the development of hardware/software
systems without using a real hardware prototype, i.e. no printed circuit
board with electronic devices such as processors, field programmable gate
arrays, peripherals and other devices is needed. The advantage is the
possibility to exchange parts in the system setup with faster turnaround
times in comparison to the traditional development process, where a time
consuming redesign of the complete board has to be done. Since some years,
the community exploiting these novel methods has grown as time to market
plays a major role in industry. Additionally, the increasing complexity
of embedded systems, which are more and more realized as parallel and
distributed cyber-physical system, forces to perform a time-consuming design
space exploration. For academics virtual prototyping is a hot topic and
is used to develop future systems and to enable an outlook into the next
generation of embedded systems and devices. The wide range of application
scenarios for this type of development includes amongst others automotive,
avionics, railway and medicine applications. This workshop targets the domain
of virtual prototyping focusing the following topics:
- Virtual prototyping development tools
- Methods for virtual prototyping of complex systems
- Application development with virtual platforms
- Methods for Hardware / Software Codesign with virtual platforms
- Design space exploration for parallel and distributed multicore and
cyber-physical systems
- Estimation of system characteristics in an early stage of development
- Functional verification at a high level of abstraction
- Methods for modeling of IP cores with SystemC
- Usage of Architecture Description Languages (ADL) for IP core development
Submission guideline
All manuscripts will be reviewed by at least three members of the program
committee. Submissions should be a complete manuscript (not to exceed 6
pages of single spaced text, including figures and tables. Submissions
should be in PDF-format. Templates for paper preparation can be found at:
http://www.ieee.org/web/publications/pubservices/confpub/AuthorTools/conferenceT...
IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a
printed volume. The complete symposium and workshop proceedings will also
be published by IEEE CS Press as a CD-ROM disk. Submitted papers should
not have appeared in or be under consideration for a different workshop
or conference. The 5 best ranked papers (according to the review results)
will be invited to submit an extended version to ACM TECS journal.
Important Dates
Submission deadline: December 21st, 2012
Decision notification: February 1st, 2013
Camera ready paper due: February 28st, 2013
The submission interface via EDAS is available under
http://edas.info/N13473
Notice to Authors By submitting your article for distribution in this Special Interest Group publication, you hereby grant to ACM the following non-exclusive, perpetual, worldwide rights: to publish in print on condition of acceptance by the editor; to digitize and post your article in the electronic version of this publication; to include the article in the ACM Digital Library and in any Digital Library related services; and to allow users to make a personal copy of the article for noncommercial, educational or research purposes. However, as a contributing author, you retain copyright to your article and ACM will refer requests for republication directly to you.
This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membership.
Circulation: 2,700
This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To unsubscribe, send an email to listserv@listserv.acm.org with "signoff sigda-announce" (no quotes) in the body of the message. Please make sure to send your request from the same email as the one by which you are subscribed to the list.
To unsubscribe from the SIGDA-announce list, click the following link:
SIGDA - The Resource for EDA Professionals
