SIGDA E-News 1 January 2013, Vol. 43, No. 1

 Special Interest Group on Design Automation
1 January 2013, Vol. 43, No. 1
Online archive:

  1. SIGDA News
        From: Lin Yuan <>
  2. What is Neuromorphic Computing?
        Contributing author:
        Yiran Chen <> University of Pittsburgh
        From: Srinivas Katkoori <>
  3. Paper Submission Deadlines
        From: Debjit Sinha <>
  4. Upcoming Conferences and Symposia
        From: Debjit Sinha <>
  5. Upcoming Funding Opportunities
        From: Prabhat Mishra <>
  6. Call for Papers: ACM TODAES Special Issue on NOCs
        From: Sudeep Pasricha <>
  7. Call for Papers: MSE 2013
        From: Laleh Behjat <>
  8. Call for Participation: TAU 2013 Variation Aware Timing Analysis Contest
        From: Debjit Sinha <>

Comments from the Editors

Dear ACM/SIGDA members,

We would like to wish all of you a very Happy New Year!

In this issue, we have a very interesting article on Neuromorphic Computing. If
you are interested in contributing to this column in the future, please
contact Srinivas Katkoori <> or Sudeep Pasricha
<>. An article only needs to be about 1 page long with
several references. All articles are included in the ACM digital library
and there is no restriction for the reproduction of the article for printed
publication later.

Sudeep Pasricha, E-Newsletter Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Prabhat Mishra, E-Newsletter Associate Editor
Srinivas Katkoori, E-Newsletter Associate Editor

Back to Contents

“Globalfoundries: Europe 'fundamentally flawed' on manufacturing”
Europe has its priorities misplaced when it comes to manufacturing, according
to Globalfoundries CEO Ajit Manocha.

“Cleantech outlook gloomy for VCs”
Venture capitalists and startup chief executives are generally lowering their
expectations about the U.S. economy in 2013 as well as market sectors including
cleantech and medical devices. However they are generally most bullish on
business and health care IT spending and Latin America, according to a
new survey.

”Servers cool it with liquid refrigerant“
Phil Hughes claims he can pack 200 KW of electronics—maybe more--into
a single server rack. A top tier OEM and a government lab are now kicking the
tires on the cooling technology of his startup, Clustered Systems Co.

“Top 10 tech blunders of 2012”
In a year that saw consolidation around several electronics ecosystems
(think Apple), 2012 also had its share of missteps (think Apple, again). In
the pages that follow, we chronicle the year’s most notable corporate delays,
false steps, miscalculations and screw-ups.

"Top 10 shifts in chips, comms"
It was a tough year. When it was all over, the semiconductor industry
contracted about four percent, according to market watchers who spent much
of the year revising their forecasts downward.

"10 Tech Gifts to Buy Your Engineer for Christmas"
Most tech-oriented holiday gift guides are for engineers, by engineers.
Unless you live with your coworkers, all that'll get you is another sweater
or a bottle of Old Spice in your stocking. Better to plop your laptop on the
dining room table so your significant other -- or your cat -- can tune in to
what you'd really like. Spoiler alert: Many of these suggestions are off the
beaten path.

"IBM details 3-D server chip stacks"
IBM will provide a deeper look into its work on 3-D chip stacks at the
International Electron Devices Meeting (IEDM) here, detailing work on stacks
of 45-nm server processors with memory and transceivers.

"Intel leapfrogs ARM (for now) with Atom server SoC"
Leaping ahead of a growing onslaught of ARM server SoCs, Intel Corp. rolled
out its dual-core, 64-bit Atom enterprise SoC, claiming 20 design wins in
microservers, comms and storage. It also said it will pack an Ethernet fabric
on to its next-generation, Avoton, a 22-nm chip shipping in 2013 that is
expected to use out-of-order cores for greater performance.

"Intel's 22-nm tri-gate SoC, how low can you leak?"
Intel will describe its 22-nm tri-gate (FinFET) SoC technology for mobile
applications Monday (Dec. 10) at the International Electron Devices Meeting
(IEDM) here.

Back to Contents

What is Neuromorphic Computing?
Yiran Chen
University of Pittsburgh

Neuromorphic Computing (also known as neuromorphic engineering) is a concept
that describes the use of very-large-scale integration (VLSI) systems to mimic
the nervous system, or called as neurobiological architecture [1]. The
establishment of neuromorphic computing research can be traced back to the
team from Caltech: Max Delbruck, Carver Mead, John Hopfield, and Richard
Feynman, each of them made significant contribution on the basic components of
neuromorphic computing: biological model, VLSI design, neural networks, and
physics of computation, respectively. In 1990, Carver Mead coined the term
“neuromoprhic” [2].

Human brain is a very ingenious and efficient computing machine. A human
brain weighs around 3 pounds and includes up to 50 billion neurons and
10^14 synapses. It offers about 100M MIPS (million-instruction-per-second)
computing capacity with only 20-40 Watts power consumption. Therefore,
conventional neuromorphic computing systems reproduce the bio-physics of
neural systems by using mixed-mode analog/digital VLSI circuitry,
e.g., designing a spike-based computing system on top of asynchronous
circuits to encode and transmit signals between computational nodes. In
spike-based computing systems, the information is communicated via spikes.
Signals are encoded in the frequency (rate), the precise timing, or the
population response of spikes. Spikes are transmitted on the chip based
on the address-event representation (AER), which is an asynchronous digital
communication protocol that sends the address of the neuron emitting the
event in real-time [3]. In some designs, the synaptic behaviors can be
modified through the training process, e.g., by programming the on-chip
capacitors or floating-gate transistors.

In human brain, every neuron connects to 2000-3000 synapses. Directly
implementing such high density interconnects is simply impossible in
current VLSI designs. Instead, the mathematical representations of biological
neural systems, known as neutral networks, are often reproduced in
neuromorphic computing chips. For example, the relationship between
the activity patterns F of the input neurons and the output neurons T
can be described in matrix form:

T = A x F (1)

where matrix A denoted as the connection matrix, which consists of the
synaptic strengths between the two neuron groups. The matrix-vector
multiplication of Eq. (1) is a frequent operation in neural network
theory to model the functionally associated neurons in brains, and
can be efficiently computed by a resistive crossbar structure: The
resistance of every cross point in the crossbar represents the weight
of the corresponding synapse. The input F is mimicked by the input
voltage vector applied to the word-line (WL) of the crossbar. The
current along every bit-line (BL) of the crossbar structure is collected and
converted to the output voltage vector T by the comparator. Matrix-vector
multiplications can be also executed by other circuit forms, such as
DRAM array [4].

The recent progress in emerging device research motivated many breakthroughs
in neuromorphic computing system implementations. As an example, memristor
device was discovered to have the capability of recording the historical
profile of the electrical excitations applied to it. The similarity between
the memristor device and biologic synapse inspired the memristor crossbar
design that can not only efficiently execute the matrix-vector multiplications,
but also flexibly train the states of the crossbar to any arbitrary values [5].
Besides memristor, spintronic device can be used to realize the same
functionality [6].

By combining the advances in nano-device, VLSI design and intelligence
algorithms, neuromorphic computing systems successfully addresses the
challenges of conventional computing system design by providing high fault
tolerance, low power consumption, small footprint and functionality
reconfigurability. Neuromorphic computing is anticipated to be widely used
in the computational intensive applications, such as spatial navigation,
object and pattern recognition, video processing, sensing networks, and
big data.


[2] G. Indiveri, “Neuromorphic VLSI Systems and Memristive Devices,”
ESSDERC Tutorial, Sep. 2012.

[3] G. Indiveri and T. K. Horiuchi, “Frontiers in Neuromorphic
Front Neurosci, vol. 5, no. 118, 2001.

[4] G. Cauwenberghs, R.T. Edwards, Y. Deng, R. Genov and D. Lemonds,
“Neuromorphic Processor for Real-Time Biosonar Object Detection,”
International Conference on Acoustics Speech and Signal Processing
(ICASSP), May 2002, pp. 3984-3987.

[5] M. Hu, H. Li, Q. Wu, and G. S. Rose. “Hardware realization of BSB
recall function using memristor crossbar arrays,” Design Automation
Conference (DAC), June 2012, pp. 498-503.

[6] M. Sharad, C. Augustine, G. Panagopoulos, and K. Roy, “Cognitive
Computing with Spin-based Neural Networks,” Design Automation Conference
(DAC), June 2012, pp. 1262-1263.

Back to Contents

Paper Submission Deadlines

BSN’13 – Int’l Conference on Wearable and Implantable Body Sensor
Cambridge, MA
Deadline: Jan 13, 2013
May 6-9, 2013

AHS’13 - NASA/ESA Conference on Adaptive Hardware and Systems
Torino, Italy
Deadline: Jan 25, 2013
Jun 24-27, 2013

DAC’13 – Design Automation Conference
Austin, TX
User track deadline: Feb 6, 2013
Jun 2-6, 2013

MSE'13 - Microelectronics Systems Education
Austin, TX
Deadline: Jan 15, 2013
Jun 2-3, 2013

PACT'13 - Int'l Conference on Parallel Architectures and Compilation
Edinburgh, Scotland
Deadline: Mar 15, 2013 (Abstracts due: Mar 11, 2013)
Sep 7-11, 2013

ASQED'13 - Asia Symposium on Quality Electronic Design
Penang, Malaysia
Deadline: Apr 23, 2013
Aug 23-28, 2013

BIOCAS'13 - Biomedical Circuits and Systems Conference
Rotterdam, Netherlands
Oct 31 – Nov 2, 2013
Deadline: Jun 14, 2013

ICFPT'13 - Int'l Conference on Field-Programmable Technology
Kyoto, Japan
Deadline: Jun 1, 2013
Dec 9-11, 2013

Back to Contents

Upcoming Conferences and Symposia

VLSI'13 - Int'l Conference on VLSI Design
Pune, India
Jan 5-10, 2013

HiPEAC'13: Int'l Conference on High Performance Embedded Architectures &
Berlin, Germany
Jan 21-23, 2013 hipeac2013

ASP-DAC'13 - Asia and South Pacific Design Automation Conference
Yokohama, Japan
Jan 22-25, 2013

ISSCC'13 - Int'l Solid-State Circuits Conference
San Francisco, CA
Feb 17-21, 2012

ISQED'13 - Int'l Symposium on Quality Electronic Design
Santa Clara, CA
Mar 11-13, 2013

DATE'13 - Design Automation and Test in Europe
Grenoble, France
Mar 18-22, 2013

ISPD’13 – Int’l Symposium on Physical Design
(co-located with TAU’13)
Lake Tahoe, CA
Mar 24-27, 2013

TAU’13 – Int’l Workshop on Timing Issues in the Specification and
Synthesis of Digital Systems
(co-located with ISPD’13)
Stateline, NV
Mar 27-29, 2013

NOCS'13 – Int’l Symposium on Networks-on-Chip
Tempe, AZ
Apr 21-24, 2013

NOCS'13 – Int’l Symposium on Networks-on-Chip
Tempe, AZ
Apr 21-24, 2013

GLSVLSI’13 – Great Lakes Symposium on VLSI
Paris, France
May 2-4, 2013

ASYNC'13 – Int’l Symposium on Asynchronous Circuits and Systems
Santa Monica, CA
May 19-22, 2013

ISCAS'13 - Int'l Symposium on Circuits and Systems
Beijing, China
May 19-23, 2013

ViPES'13 - Workshop on Virtual Prototyping of Parallel and Embedded Systems
Boston, MA
May 24, 2013

HOST'13 – International Symposium on Hardware-Oriented Security and Trust
Austin, TX
June 2-3, 2013

ISCA’13 – Int’l Symposium Computer Architecture
Tel-Aviv, Israel
Jun 23-27, 2013

Back to Contents

Upcoming Funding Opportunities


Office of Naval Research (ONR) Sabbatical Leave Program
Deadline: Continuous

Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Deadline: Continuous


Strategic Technology Office (STO) Broad Agency Announcement (BAA)
Deadline: January 12, 2013

Microsystems Technology Office-Wide Broad Agency Announcement
Deadline: September 1, 2014


Young Investigator Program (YIP)
Deadline: January 4, 2013

Research Interests of the Air Force Office of Scientific Research
Deadline: Continuous

High Performance Computing on Massively Parallel Architectures (BAA 64-09-01)
Deadline: Continuous


Director's Postdoctoral Fellows
Deadline: Continuous

Postdoctoral Appointments
Deadline: N/A

Sabbaticals and Faculty Appointments
Deadline: continuous

McDonnell Foundation

Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Deadline: continuous


National Robotics Initiative (NRI)
Deadline: January 23, 2013 (large)

Cyber-Physical Systems (CPS)
Deadline: January 29, 2013

Exploiting Parallelism and Scalability (XPS)
Deadline: February 20, 2013

Core Techniques and Technologies for Advancing Big Data Science & Engineering
Deadline: June 13, 2013


Young Investigator Program (YIP)
Deadline: Jan 4, 2013


Ralph E. Powe Junior Faculty Enhancement Awards
Deadline: January 11, 2013

Back to Contents

Call for Papers: ACM TODAES Special Issue on NOCs

ACM Transactions on Design Automation on Electronic Systems Special Section on
Networks on Chip: Architecture, Tools, and Methodologies

Continuous technology scaling has enabled the integration of hundreds of
processing cores on the same silicon substrate, therefore allowing for the
concurrent execution of multiple applications on a chip. For such systems,
traditional solutions for on chip communication are likely unable to scale,
thereby requiring a departure from classic on-chip communication paradigms. The
Networks-on-Chip (NoC) approach has emerged as the most promising
communication paradigm for massively integrated multicore systems. This
special section will report on recent advances in development of on-chip
communication technology, architecture, design methods and applications while
encouraging innovation from inter-related research communities, including
computer architecture, networking, circuits and systems, embedded systems,
and design automation. Topics of interest include, but are not limited to:

- Network architecture (topology, routing, arbitration)
- Network design for 3D stacked logic and memory
- Mapping of applications onto NoCs
- Power and energy issues
- Timing, synchronous/asynchronous communication
- NoC reliability issues
- OS support for NoCs
- Programming models
- Multi/many-core workload characterization & evaluation
- Network interface issues
- NoC case studies, application-specific NoC design
- Modeling, simulation, and synthesis of NoCs
- NoC support for memory and cache access
- NoC design methodologies and tools
- NoC Quality of Service
- NoCs for FPGAs and structured ASICs
- NoC support for CMP/MPSoCs
- Novel interconnect links/switches/routers
- Optical & RF for on-chip/in-package interconnects
- Signaling and circuit design for NoC links
- Physical design of interconnect and NoC
- Verification, debug & test of NoCs
- Metrics and benchmarks for NoCs

Authors are encouraged to submit high-quality research contributions that will
not require major revisions. Extensions of papers presented at the NOCS’12
– the International Symposium on Networks on a Chip, Copenhagen, Denmark,
May 9-11, 2012 ( ) are especially encouraged. Please
identify clearly the additional material from the original symposium paper
in your submitted manuscript. Submissions of relevant original work not
presented at NOCS’12 are also welcome. All manuscripts are subject to
standard ACM Transactions on Design Automation of Electronic Systems review
process. Prospective authors should submit their manuscripts electronically
on the TODAES Web site:

Authors should clearly identify their papers as submissions for the “Special
Section on NOC:ATM 2012” on their manuscript and in the Note to Editor
field of the web submission form. Instructions on how to submit a paper can
be found at and authors can contact
Annie Yu at for further assistance.

Important Dates:

Submission Deadline: January 18, 2013
Notification Date: April 26, 2013
Final Version Due: June 7, 2013

Guest Editors:

Diana Marculescu
Carnegie Mellon University
Pittsburgh, PA

Chita Das
Penn State University
State College, PA

Back to Contents

Call for Papers: MSE 2013

Call for Papers: 9th IEEE International Conference on Microelectronic Systems
Education (MSE 2013)

June 2 – 3, 2013, Austin, Texas


The IEEE Computer Society International Conference on Microelectronic Systems
Education is the premier
conference dedicated to furthering undergraduate and graduate education in
designing and building innovative
microelectronics systems. The conference is held in the U.S. in odd years,
and in Europe in even years, when it is called the

European Workshop on Microelectronics Education (EWME). MSE is co-located
with the Design Automation Conference (DAC) providing the participants with a
unique opportunity to attend both conferences.

Topics of Interest

The MSE conference provides an excellent opportunity for educators and
industry to work together to ensure continued excellence in the field of
microelectronic systems. Of particular interest is incorporation of emerging
trends in the microelectronic system industry and research into the classroom.

Papers are invited in (but not limited to) the following areas:

- Pedagogical innovations using a wide range of technologies, including
nanometer-scale integrated circuits, low-power design, nanotechnology,
application-specific integrated circuits(ASICs), field programmable gate
arrays (FPGAs), multicore/many-core processors, graphics processing units
(GPUs), sensor networks, and embedded systems.
- Educational techniques including novel curricula and laboratories,
assessment methods, distance learning, textbooks, and design projects.
- Industry and academic collaborative programs and teaching.
- Preparing students for industry, entrepreneurship, academics, and/or

Papers submitted to MSE 2013 should not exceed four (4) pages in
length. Submissions must comply with IEEE Computer Society formatting
requirements. Submissions in PDF or postscript format may be submitted
on-line at Submissions will be judged on
originality, appropriateness, technical strength, assessment,
and other relevant criteria.

Important Dates
Submission of papers: January 15, 2013
Notification of acceptance: March 15, 2013
Submission of final papers: April 8, 2013

General Chair
John Nestor
Lafayette College

Program Chair
Matthew R. Guthaus
University of California, Santa Cruz

Back to Contents

Call for Participation: TAU 2013 Variation Aware Timing Analysis Contest

TAU 2013 ( invites you to participate in a software tool
development contest on variation aware parametric timing analysis. With the
increasing number and significance of manufacturing and environmental sources
of variability in the design and use of modern VLSI designs, timing analysis
considering the uncertainty due to variability is essential. At the same time,
the growing complexity of modern designs requires fast timing analysis, thereby
requiring tools to adopt accuracy and run-time tradeoffs. The goals of this
contest are the following.

* Motivate university level students to learn about modern VLSI design timing
analysis in the presence of variability and encourage research in this area
* Provide insight to some challenging aspects of a "fast" parametric
(e.g. statistical) static timing analysis tool, and look for novel solutions,
the results of which may be interesting to both industry and academia
* Encourage use of parallel techniques for timing analysis (especially
multi-threaded techniques)
* Facilitate creation of a public university level variation aware timer
(would serve as a framework for contests in future)

Contestants would be asked to additionally provide a presentation (.ppt
or .pdf) describing key novel contributions of their tool. The top three
contestants would be invited to present their work as part of the TAU-20
talks. Look out for contest details and details on "surprise" awards for the
top contestants on the website:

Contest specifications, sample benchmarks, and a cell library are available
on the contest website. Upon request, a deterministic timer infrastructure is

• Contest announced: October 12, 2012
• Early binaries due (for verification/initial feedback): February 1, 2013
• Final version of binaries due with 2 page document describing key ideas:
February 15, 2013
• Results announced: March 27, 2013 (at TAU workshop)

All communication regarding the TAU 2013 contest (including contest
registration) must be directed to Contest organizers:

• Dr. Debjit Sinha, IBM Corp. (Chair)
• Prof. Luis Guerra e Silva, INESC-ID / IST - TU Lisbon, Portugal
• Prof. Jia Wang, Illinois Institute of Technology,
• Dr. Shesha Ragunathan and Mr. Dileep Netrabile, IBM Corp.
• Dr. Ahmed Shebaita, Synopsys Inc.

Back to Contents

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