Problems and References (CADathlon 2012)

 
 
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To download the tar.gz file for all related papers, click here.
 
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Problem 1: Circuit Design & Analysis
 
Contributed by: Logan Rakai, University of Calgary
 
Overview: Gate sizing using geometric programming
 
S. Boyd, S.-J. Kim, L. Vandenberghe, A. Hassibi, "A Tutorial on Geometric Programming," Optimization and Engineering, 8(1), 2007, pp. 67-127.
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Problem 2: Physical Design
 
Contributed by: Shiyan Hu, Michigan Tech
 
Overview: Slew constrained minimum cost buffer insertion
 
Buffer insertion is an important optimization technique in the VLSI physical design flow and the students will be asked to implement the slew constrained minimum cost buffer insertion algorithm in the reference paper. The students should focus on Section 3.1 which is about standard dynamic programming based slew buffering assuming that the input slew at each buffer is fixed.
 
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang Karandikar, Zhuo Li, Weiping Shi, C. N. Sze, "Fast algorithms for slew constrained minimum cost buffering," in Proceedings of the Design Automation Conference, pp. 308-313, 2006.
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Problem 3: Logic & High-Level Synthesis
 
Contributed by: Shilpa Pendyala and Srinivas Katkoori, University of South Florida
 
Overview: Interval Propagation of minimum leakage intervals using interval arithmetic.
 
Shilpa Pendyala, Srinivas Katkoori, "Interval Arithmetic Based Input Vector Control for RTL Subthreshold Leakage Minimization," in IEEE/IFIP 20th International Conference on Very Large Scale Integration (VLSI-SOC), October 2012.
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Problem 4: System Design and Analysis
 
Contributed by: Nishit Kapadia and Sudeep Pasricha, Colorado State University
 
Overview: On-chip power delivery network design in 3D chip-multiprocessors with multiple voltage islands
 
N. Kapadia, S. Pasricha, "A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands," in Proc. VLSI Design 2012, pp. 262-267.
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Problem 5: Functional Verification
 
Contributed by: Samar Abdi, Concordia University, Montreal
 
Overview: SystemC Modeling of OS Scheduler
 
A. Gerstlauer, H. Yu. D. Gajski, "RTOS Modeling for System-Level Design," Design Automation and Test in Europe (DATE) Conference 2003.
 
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Problem 6: Bio EDA
 
Contributed by: Jason Gallia and Patrick Madden, Binghamton University
 
Overview: Building an amino acid Sequence through De Novo sequencing
 
K.R. Jonscher, "Validating Sequence Assignments for  Peptide Fragmentation Patterns: A Primer in MS/MS Sequence Identification," Proteome Software, 2005.
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Computer Platform

 
During the contest one desktop computer will be available per team, running a standard installation of Ubuntu Linux. All necessary software and the problem statements will be pre-installed. In your home directory you will find a beginning directory structure to organize your work and initial problem frameworks such as parsers.

You will be allowed to bring in any written or printed materials, but no electronic storage media or computing devices. (If you have a preferred VIM or Emacs configuration, you will need to print them out beforehand and type them in.) Whatever you bring in shall stay in the room until you decide to leave the room at the end of the day.

You will not have any internet or phone access during the competition, and you are expected not to discuss any questions with colleagues other than your team member.
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