Problems and References

 
Problem 1: Circuit Design & Analysis
Contributed by Dr. Frank Liu (IBM) and Myung-Chul Kim (IBM)
Overview: Weibull delay computation
F. Liu, C. Kashyap, C. Alpert, "A delay metric for RC circuits based on the Weibull distribution", IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 620-624, 2002.
Graph-Template Library (GTL), https://github.com/rdmpage/graph-template-library
Bisection method, https://en.wikipedia.org/wiki/Bisection_method
 
Problem 2: Physical Design
Contributed by: Bei Yu (Chinese Univ. of Hong Kong)
Overview: Triple Patterning Aware Detailed Placement
B. Yu, X. Xu, J.-R. Gao, Y. Lin, Z. Li, C. Alpert and D. Z. Pan, "Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.34, no.5, pp.726-739, 2015.
 
Problem 3: Logic & High-Level Synthesis
Contributed by Dr. Myung-Chul Kim (IBM)
Overview: Technology mapping (structural/boolean matching)
No specific reference.
 
Problem 4: System Design and Analysis
Contributed by: Dr. Xiang Chen (George Mason University) and Dr. Jingtong Hu (Oklahoma State University)
Overview: Dynamic Voltage Scaling for OLED Display
X. Chen, M. Zhao, J. Zeng, C. J. Xue and Y. Chen, "Quality-retaining OLED Dynamic Voltage Scaling for Video Streaming Applications on Mobile Device,” Design Automation Conference (DAC), page: 1000-1005, Jun 2012.
 
Problem 5: Verification
Contributed by: Jacky Hsu (Cadence)
Overview: Solving QBF2 by 2 SAT solver
a. K.-F. Tang, et al. "Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction." in Proc. Design, Automation and Test in Europe Conference & Exhibition (DATE), pp. 1567-1572, Mar 2012,
b. C.-F. Lai, et al. "BooM: a decision procedure for boolean matching with abstraction and dynamic learning." in Proc. ACM/EDAC/IEEE Design Automation Conference (DAC), June 2010, pp. 499-504.
c. A. Biere "The AIGER And-Inverter Graph (AIG) Format Version 20071012", URL http://fmv.jku.at/aiger/FORMAT.aiger
d. N. En and N. Srensson. "The minisat page." Online. URL http://minisat.se/Main.html (2012).
 
Problem 6: Future technologies (Security)
Contributed by: Dr. Yier Jin (University of Central Florida) and Dr. Jingtong Hu (Oklahoma State University)
Overview: Netlist Reverse Engineering (Python)
T. Meade, S. Zhang, and Y. Jin, "Netlist reverse engineering for high-level functionality reconstruction,” 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 655-660, 2016.