Problems and References

 
Problem 1: Circuit Design & Analysis
Contributed by Tsung-Wei Huang (UIUC)
Overview:  Path-based Timing Analysis (in C++)
J. Y. Yen, "Finding the k-Shortest Loopless Paths in a Network", Management Science, vol. 17, no. 11, pp. 712--716, July 1971. http://people.csail.mit.edu/minilek/yen_kth_shortest.pdf
 
Problem 2: Physical Design
Contributed by Hua-Yu Chang (Synopsys)
Overview: Timing Optimization via Bezier Curve Smoothing (in C/C++)
a. H.-Y. Chang, I. H.-R. Jiang, and Y.-W. Chang, "Timing ECO optimization via Bezier curve smoothing and fixability identification," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 12, Dec. 2012, pp. 1857--1866.
b. http://mathworld.wolfram.com/BezierCurve.html
 
Problem 3: Logic & High-Level Synthesis
Contributed by Myung-Chul Kim (IBM)
Overview: Technology mapping (structural/boolean matching) (in C/C++)
No specific reference.
 
Problem 4: System Design and Analysis
Contributed by Andy Yu-Guang Chen (Yuan Ze University)
Overview: Placement of Multi-Bit Retention Registers (in C)
a. Y.-G. Chen, H. Geng, K.-Y. Lai, Y. Shi, and S.-C. Chang, 2014, April, "Multi-Bit Retention Registers for Power Gated Designs: Concept, Design and Deployment," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 4, pp. 507--518, April 2014.
b. P. Ashar, and S. Malik, "Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications", in Proc. Design Automation Conference (DAC), 1994, pp. 77--80.
 
Problem 5 Verification
Contributed by Hao Zheng (University of South Florida)
Overview: Cycle-based logic simulation (in C/C++)
a. S. Palnitkar and D. Parham, "Cycle Simulation Techniques," IEEE International Verilog HDL Conference, 1995, pp. 2--8.
b. A. Biere "The AIGER And-Inverter Graph (AIG) Format Version 20070427
 
Problem 6 Future technologies
Contributed by Chung-Wei Lin (National Taiwan University)
Overview: Timing Analysis for Controller Area Network (in C)
R. I. Davis, A. Burns, R. J. Bril, J. J. Lukkien, "Controller Area Network (CAN) schedulability analysis: Refuted, revisited and revised," in Real-Time Systems, vol. 35, no. 3, pp. 239--272, Apr. 2007.
(We expect the participants to read, at least, the first three sections, i.e., about 20 pages, of the paper.)
 

Computer Platform
During the contest one desktop computer will be available per team, running a standard installation of Ubuntu Linux. All necessary software and the problem statements will be pre-installed. You will be allowed to bring in any written or printed materials, but no electronic storage media or computing devices. (If you have a preferred VIM or Emacs configuration, you will need to print them out beforehand and type them in.) Whatever you bring in shall stay in the room until you decide to leave the room at the end of the day. You will not have any internet access during the competition, and you are expected not to discuss any questions with colleagues other than your team member.