SIGDA E-News 1 April 2011, Vol. 41, No. 4

 Special Interest Group on Design Automation
1 April 2011, Vol. 41, No. 4
Online archive:

  1. SIGDA News
        Contributing author: Marc Riedel <>
        Contributing author: Lin Yuan <>
  2. What is Cloud Computing?
        Contributing author: D. Cenk Erdil <>
        From: Mehmet Yildiz <>
  3. Paper Submission Deadlines
        From: Debjit Sinha <>
  4. Upcoming Conferences and Symposia
        From: Debjit Sinha <>
  5. Upcoming Funding Opportunities
        From: Sudeep Pasricha <>
  6. Call for Demonstrations: ACM/SIGDA University Booth at DAC
        From: Naehyuck Chang <>
  7. Call for Papers: 5th IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y 2011)
        From: Jingwei Lu <>
  8. Call for Papers: The 3rd International Workshop on Bio-Design Automation
        From: Leonidas Bleris <>
  9. Call for Submissions: SIGDA Ph.D. Forum at the Design Automation Conference
        From: Philip Chong <>
  10. Call for Papers: The First International IEEE Workshop on Thermal Modeling and Management: Chips to Data Centers
        From: Sherief Reda <>
  11. Call for Submissions: Second ACM Student Research Competition at the ACM/IEEE Design Automation Conference
        From: Naehyuck Chang <>
  12. Call for Papers: Journal of ECE Special Issue on ESL Design Methodology
        From: Deming Chen <>
  13. Call for Participation: 1st CRA-W/CDC Workshop on Diversity in Design Automation and Test
        From: Diana Marculescu <>
  14. Call for Papers: 19th IFIP/IEEE International Conference on Very Large Scale Integration
        From: Matthew Guthaus <>

Comments from the Editors

Dear ACM/SIGDA members,

This month we are re-publishing the contribution from
Asst. Prof. D. Cenk Erdil from Ä°stanbul Bilgi University on "What is
Cloud Computing?". If you are interested in writing a "What is..."
column for a future issue, please contact Associate Editor Mehmet
Yildiz <>.

Please welcome our newest Associate Editor Srinivas Katkoori
<> from University of South Florida. Srinivas will
be helping with the SIGDA News and general proof reading of other

Matthew Guthaus, E-Newsletter Editor;
Marc Riedel, E-Newsletter Associate Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Umit Y Ogras, E-Newsletter Associate Editor;
Sudeep Pasricha, E-Newsletter Associate Editor;
Mehmet Yildiz, E-Newsletter Associate Editor;
Srinivas Katkoori, E-Newsletter Associate Editor

Back to Contents


CPUs in FPGAs: many faces to a trend
Whether as synthesizable soft cores or hard cores on the die, CPUs are
showing up in more FPGA designs, bringing with them important
challenges for designers. Both hard and soft CPU cores are available
to FPGA users. CPU cores can serve a range of purposes in an FPGA
design. The vendor’s view of the purpose has influenced tools and
support for individual cores.

48th Design Automation Conference to Feature Keynote Interview
by Apple Computer, Inc. Co-founder Steve Wozniak
Steve Wozniak, co-founder of Apple Computer, Inc., and Chief
Scientist, Fusion-IO, will keynote at the 48th Design Automation
Conference (DAC), the worldwide premier event devoted to design and
design automation of electronic systems (EDA). Steve will be
interviewed live on stage by San Jose Mercury News columnist Mike
Cassidy on a wide range of topics, including the ‘joy’ of engineering
and following your passion to convert innovative ideas into reality.

Making Cellular Memories
Cells permanently change their behavior in response to temporary
changes to the environment, a kind of biological memory that controls
processes as important and complex as how stem cells differentiate
into specific tissues or how the immune system "remembers" dangerous
pathogens. At its simplest, cellular memory is achieved with a
positive feedback loop--once activated by some external signal, the
feedback loop will continually activate itself, even as the cell
divides and the signal is taken away. In synthetic biology we can
recreate such simple feedback loops, genetic circuits built of parts
that activate in response to signals and keep turning themselves on,
remembering past chemical events.

Researchers claim extremely sensitive sensor based on Raman scattering
The university describes the sensor as being able to boost faint
signals generated by the scattering of laser light from a material
placed on it, allowing the identification of various substances based
on the color of light they reflect.

Complete IC simulation requires a full toolbox of hardware and software
Combining faster solvers with test benches that link analog to digital
to system-level models prevents design errors.

EDA growth hit double-digits again in Q4
EDA revenue for the fourth quarter of 2010 totaled nearly $1.51
billion, up 15 percent compared with the third quarter and up 19
percent compared to the fourth quarter of 2009, double-digit increases
for the second consecutive quarter, according to the EDA Consortium

Synopsys preps 'surge' verification via cloud
EDA and IP vendor Synopsys Inc.'s top executive said Monday (March 28)
that Synopsys would leverage the power of cloud computing to offer
verification services on a massive scale by putting hundreds or even
thousands of computers to work at one time on running simulations on
customer designs using its VCS Verilog compiled code simulator.

Back to Contents

What is Cloud Computing?

Asst. Prof. D. Cenk Erdil, Istanbul Bilgi University

From field-programmable gate arrays to advanced service-oriented architectures,
cloud computing owes its existence to a number of technological advances and
novel approaches that almost happened together within the last decade.

Looking from an academic point of view, we can attest that cloud computing is
mere example of what grid computing promised in the 1990s, i.e., “ubiquitous,
seamless access to the vast computing power available everywhere” [1]. Looking
from an IT person’s point of view, on the other hand, a-la-cloud is a novel
approach for business-centric computing [2].

Clouds can simply be categorized as public (open to anyone) and private
(organizational) clouds. Perhaps one widely known public cloud example is
Amazon’s Elastic Compute Cloud (EC2) that provides “resizable compute capacity”
in the cloud [3]. A good example of a research-oriented private cloud can be
the Enabling Grids for E-sciencE (EGEE) project [4] and the LHC Computing Grid,
that support processing experimental data from CERN’s Large Hadron Collider.
These two grids together use state-of-the-art technologies and novel computing
methods that will also set the path to what cloud computing will have to offer
in the next several years.

Current definition of cloud computing is constituted by three layers between a
client and a server, Application, Platform, and Infrastructure (Hardware),
1) Software as a Service (SaaS): centralized management and distributed
delivery stack of applications on the Internet,
2) Platform as a Service (PaaS): a computing stack that consumes infrastructure
and applications on the cloud,
3) Infrastructure as a Service (IaaS): a mechanism to access computational
resources of service providers.

Several technologies and related concepts can be attributed as key enabling
technologies of cloud computing. Among these are:
* Virtual Organizations: an eclectic group of individuals and/or institutions
that share a common set of resources in coordination,
* Virtualization: An enabling mechanism for more efficient computing resource
utilization, both for providers and requesters,
* Autonomic Computing (automated self-provisioning): makes it possible for
resources to self-manage themselves with minimal human administration,
* Service-Oriented Architecture: allows resources to be utilized seamlessly,
i.e., without a direct reference to the underlying hardware,
* Utility Computing: is a pay-as-you-go model computing, where organizations
make use of computing resources as they need, and ideally, do not own any
particular resources,
* Multi-core architectures: makes virtualization and utility computing easier
with dedicated cores to each particular cloud service,
* Sensor Networks: with their low-powered ubiquitous sensing devices, or
motes, they make autonomic computing and scalability possible for core cloud
services, such as resource scheduling, and so on,
* Optical Fiber: acts as a waveguide in its thin, flexible and fiber form to
transmit light between two ends, permitting transmission over longer
distances and higher data rates,
* Social Networks: closes some of the gaps in cloud computing, in particular
in the trust and security areas, that have long been unanswered by grids and
clouds to date.

In summary, cloud computing is a novel approach that brings together what
earlier distributed computing incarnations have not made possible yet. Some
consider it the next IT-marketing hype, some have already made it their primary
research field. Whatever your take, cloud computing will be making itself
available as part of your daily technical dose for the next decade or so.

[1] Grimshaw, A., et al., “The Legion Vision of a Worldwide Virtual Computer”,
Communications of the ACM, v.40, n.1, p.39-45, Jan 1997.
[2] Ratcliffe, D., and Shillito, P., “Could the cloud drive a more business-
centric approach to security?”, Fujitsu Insights and Opinions, The Telegraph,
18 Jan 2011.
[3] Amazon Team, “Getting Started Guide (API Version 2010-11-15)”,, Accessed
on Feb 19, 2011.
[4] Erwin, L., and Jones, B., “Enabling Grids for E-Science: The EGEE Project”,
EGEE-PUB-2009-001, 2009.

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Paper Submission Deadlines

DFM&Y'11 - Int'l Workshop on Design for Manufacturability & Yield
San Diego, CA (Co-located with DAC)
Jun 6, 2011
Deadline: Apr 3, 2011

ASQED'11 - Asia Symposium on Quality Electronic Design
Kuala Lumpur, Malaysia
Jul 19-20, 2011
Deadline: Apr 4, 2011

IWBDA'11 - Int'l Workshop on Bio-Design Automation
San Diego, CA (Co-located with DAC)
Jun 6-7, 2011
Deadline: Apr 5, 2011

ESWEEK'11 - Embedded Systems Week (CASES, CODES+ISSS, and EMSOFT)
Taipei, Taiwan
Oct 9-14, 2011
Deadline: Apr 11, 2011 (Abstracts due: Apr 4, 2011)

VLSI-SoC’11 – Int’l Conference on Very Large Scale Integration and System on Chip
Hong Kong, China
Oct 3-5, 2011
Deadline Apr 14, 2011

ICCAD’11 – Int’l Conference on Computer-Aided Design
San Jose, CA
Nov 6-10, 2011
Deadline: Apr 18, 2011

Wireless Health’11
San Diego, CA
Oct 10-13, 2011
Deadline: Apr 22, 2011 (Abstracts due: Apr 15, 2011)

24th ACM SIGDA University Booth
(co-located with DAC’11)
San Diego, CA
Jun 5 - 10, 2011
Deadline: May 2, 2011 (tentative)

HiPC'11 - Int'l Conference on High Performance Computing
Bangalore, India
Dec 18-21, 2011
Deadline: May 16, 2011

MICRO'11 - Int'l Symposium on Microarchitecture
Porto Alegre, Brazil
Dec 3-7, 2011
Deadline: May 25, 2011

ICFPT'11 - Int'l Conference on Field-Programmable Technology
Delhi, India
Dec 12-14, 2011
Deadline: Jun 8, 2011

BodyNets'11 – Int’l Conference on Body Area Networks
Beijing, China
Nov 7-10, 2011
Deadline: May 31, 2011

HLDVT’11 – Int’l High-Level Design, Validation and Test Workshop
Napa Valley, CA
Nov 9-11, 2011
Deadline: Jun 10, 2011

BIOCAS'11 - Biomedical Circuits and Systems Conference
San Diego, CA
Nov 10-12, 2011
Deadline: Jun 10, 2011

ISED’11 – Int’l Symposium on Electronic System Design (co-located with Int’l Workshop on Embedded Computing and Communication)
Kochi, India
Dec 19-21, 2011
Deadline: Jun 15, 2011

ICPADS'11 - Int'l Conference on Parallel and Distributed Systems
Tainan, Taiwan
Dec 7-9, 2011
Deadline: Jun 24, 2011

ASP-DAC'11 - Asia and South Pacific Design Automation Conference
Sydney, Australia
Jan 30 - Feb 2, 2012
Deadline: Jul 19, 2011

Back to Contents

Upcoming Conferences and Symposia

SPL'11 - Southern Conference on Programmable Logic
Cordoba, Argentina
Apr 13-15, 2011

ASYNC'11 - Intl. Symposium on Asynchronous Circuits and Systems
Ithaca, NY
Apr 27-29, 2011

ISCAS'11 - Int'l Symposium on Circuits and Systems
Rio De Janerio, Brazil
May 15-18, 2011

ISCA’11 – Int’l Symposium Computer Architecture
San Jose, CA
Jun 4-8, 2011

SLIP’11 - System Level Interconnect Prediction
San Diego, CA
June 5, 2011

DAC’11 – Design Automation Conference
San Diego, CA
Jun 5-10, 2011

SASP’11 – Symposium on Application Specific Processors
(co-located with DAC’11)
San Diego, CA
Jun 5-6, 2011

AHS’11 - NASA/ESA Conference on Adaptive Hardware and Systems
(co-located with DAC’11)
Jun 6-9, 2011
San Diego, CA

MSE'11 - Microelectronics Systems Education
San Diego, CA (co-located with DAC’11)
Jun 5 - 6, 2011

24th ACM SIGDA University Booth
(co-located with DAC’11)
San Diego, CA
Jun 5 - 10, 2011

MEMOCODE'11 – Int’l Conference on Formal Methods and Models for Codesign
Cambridge, United Kingdom
Jul 11-13, 2011

ETMEC'11 - Int'l Workshop on Energy and Thermal Management of Embedded Computing
Maui, Hawaii
Jul 31 - Aug 4, 2011

VLSI-SoC’11 – Int’l Conference on Very Large Scale Integration and System on Chip
Hong Kong, China
Oct 3-5, 2011

PACT'11 - Int'l Conference on Parallel Architectures and Compilation
Galveston Island, TX
Oct 8-12, 2011

Back to Contents

Upcoming Funding Opportunities


Office of Naval Research (ONR) Sabbatical Leave Program
Deadline: N/A

Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Deadline: Continuous


Microsystems Technology Office-Wide Broad Agency
Announcement - DARPA-BAA-10-35
Deadline: Continuous


Biomimetic Signal Processing and Control - BAA-RWK-10-0001
Deadline: Continuous through April 30, 2011

Hardware-in-the-Loop Simulation Technologies - BAA-RWK-10-0001
Deadline: Continuous through April 30, 2011

ARL/ARO Core Broad Agency Announcement for Basic and Applied
Scientific Research for Fiscal Years 2007 through 2011
Deadline: Continuous through September 30, 2011

Robust Computational Intelligence - AFOSR-BAA-2010-01
Deadline: Continuous

Systems and Software - AFOSR-BAA-2010-01
Deadline: Continuous

ERDC BAA - Computational Science and Engineering (ITL-1)
Deadline: Continuous

Advanced Distributed Sensor Technologies - BAA 57-09-06
Deadline: Continuous

Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
Deadline: Continuous

High Performance Computing on Massively Parallel Architectures
(BAA 64-09-01)
Deadline: Continuous

ASEE-NRL Postdoctoral Fellowship Program
Deadline: N/A


Postdoctoral Appointments
Deadline: N/A

McDonnell Foundation

Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Deadline: continuous


Emerging Frontiers in Research and Innovation 2011 (EFRI-2011) - NSF 10-596
Deadline: April 01, 2011

Expeditions in Computing – NSF 10-564
Deadline: May 10, 2011

Research Coordination Networks (RCN) – NSF 11-531
Engineering and Education for Sustainability (RCN-SEES) track
Deadline: May 24, 2011

Cyberlearning: Transforming Education – NSF 10-620
Deadline Date: May 14, 2011 (letter of intent)

Science and Technology Centers: Integrative Partnerships – NSF 11-522
Preliminary Proposal Deadline Date: May 30, 2011
Full Proposal Deadline Date: February 3, 2012

Industry/University Cooperative Research Centers Program (I/UCRC) – NSF 10-595
Letter of Intent Deadline Date: June 26, 2011
Full Proposal Deadline Date: September 26, 2011

Faculty Early Career Development (CAREER) Program – NSF 11-690
Full Proposal Deadline Date: July 25, 2011 (BIO, CISE, EHR, OCI)
Full Proposal Deadline Date: July 26, 2011 (ENG)


Research in Environment, Safety & Health
Deadline (white paper): Thursday, April 14, 2011

Research in Back End Processes, Packaging, and Interface
Deadline (white paper): Wednesday, May 4, 2011

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Call for Demonstrations: ACM/SIGDA University Booth at DAC

Call for Demonstration

24th ACM SIGDA University Booth
at the 48th Design Automation Conference
San Diego Convention Center
San Diego, California
June 5-10, 2011

This year marks the 24th University Booth at the Design Automation
Conference. The booth is an opportunity for university researchers to
display their results and to interact with participants at
DAC. Presenters and attendees at DAC are especially encouraged to
participate, but participation is open to all members of the
university community. The demonstrations include new EDA tools, EDA
tool applications, design projects, and instructional materials.

* The university booth will be located near the technical sessions for
improved visibility.

* The university booth will be open two full days. June 7th - 8th:
10am - 5pm.

* The submission is in a 5-min video presentation format. Live
demonstrations performed at the booth by university researchers
simultaneous with the video presentations. Submitted video are
considered for publications in the ACM Digital Library. Also, it
will be featured on the DAC and SIGDA web pages, and be available

* Participants at the University Booth are also provided with modest
travel grant reimbursements, provided that posters are hung for the
entire duration of the conference and that demonstrations are
completed during the time slots that they are
scheduled. Participants who receive funding for the conference via
alternative sources such as the Ph.D. forum and Student Design
Contest are not eligible for travel grants through the University

Tentative Deadline for registration is May 2, 2011

To apply for participation, please visit the University Booth website
( ) Video demonstrations should
include a brief title sequence identifying the name of the research
group and university, the team members, and stating "SIGDA University
Booth at DAC 2011". Otherwise, there is complete freedom in how a
group wishes to present their work. A sample video is available on
Youtube ( )

Booth Coordinators

Naehyuck Chang (
Baris Taskin (
Joe Zambreno (

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Call for Papers: 5th IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y 2011)

5th IEEE International Workshop on
Design for Manufacturability & Yield (DFM&Y 2011)
San Diego Convention Center, San Diego, California, USA
June 6, 2011

Co-located with the 48th Design Automation Conference

********* Preliminary Call for Papers *********

Scope: Increased manufacturing variability in leading-edge process
technologies requires new paradigms and solution technologies for
yield optimization. SoC manufacturability and yield entails design-
specific optimization of the manufacturing, and thus enhanced
communications across the design-manufacturing interface. A wide
range of Design-for-Manufacturability (DFM) and Design-for-Yield
(DFY) methodologies and tools has been proposed in recent years.
Some of these tools are leveraged during back-end design, others
are applied just before manufacturing handoff, and still others are
applied post-design, from reticle enhancement and lithography
through wafer sort, packaging, final test and failure analysis. DFM
and DFY can dramatically impact the business performance of chip
manufacturers. It can also significantly affect age-old chip design
flows. Using DFM and DFY solutions is an investment, and choosing
the most cost effective one(s) requires careful analysis of
integration and schedule overheads, versus quantified benefits.
This workshop analyzes this key trend and its challenges, and
provides an opportunity to discuss a range of DFM and DFY solutions
for today’s SoC designs.

Representative topics include, but are not limited to:

* Electrical, Design-Driven DFM
* Built-in Repair Analysis and Self-Repair
* Adaptive Design Techniques in DFM/DFY
* Embedded Test and Diagnosis
* OPC and RET
* DFM for 3D Integration
* DFM at System/Architecture Level
* Analog and Mixed-Signal DFM
* Process Monitoring IP
* Statistical Design
* Test-based Yield Learning
* Design-Aware Manufacturing
* Yield Enhancement IP
* Yield Management

Information for Authors:

To present at the Workshop, authors are invited to submit
unpublished extended abstracts or full papers, 2 to 4 pages in
length. Submissions on ambitious works in progress are also
encouraged. Each submission should include a short abstract of 50
words, and keywords. The review process is blind. Please do not
include author names or affiliations. Proposals for embedded
tutorials and panel discussions are also invited. Submit a copy of
your paper proposal as a PDF at

The goal of the workshop is to foster unrestricted discussion in
the field of design-manufacturing interactions. Copies of papers
will be provided to attendees in the form of Workshop Notes, but no
proceedings will be published. Therefore, accepted papers can still
be submitted to other conferences and journals.

***** Submissions are due no later than April 3rd, 2011 *****

Authors will be notified of the disposition of their papers by
April 25th, 2011. Authors of accepted papers must submit an
illustrated text by May 15th, 2011 for inclusion in the Workshop
Notes, which will be provided to the attendees.

DFM&Y 2011 is sponsored by the IEEE Computer Society Test
Technology Technical Council (TTTC) in cooperation with the IEEE
Council on Electronic Design Automation (CEDA). For more
information on DFM&Y 2011, visit the workshop website at:

Program Organizers

General Chair
R. Aitken, ARM

Program Chair
P. Gupta, UCLA


Steering Committee
A. B. Kahng, UCSD
A. Singh, Auburn Univ.
Y. Zorian, Synopsys

Program Committee
S. Datla, Texas Instruments
A. Gattiker, IBM
P. Gupta, UCLA
A. B. Kahng, UCSD
V. Moroz, Synopsys
N. S. Nagaraj, Texas Instruments
M. Orshansky, Univ. of Texas
D. Pan, Univ. of Texas
C.-H. Park, Samsung
J.M. Portal, Univ. of Marseilles
T. Quan, TSMC
T. Shibuya, Fujitsu
A. Singhee, IBM
R. Topaloglu, Global Foundries
A. Torres, Mentor Graphics

For general information contact:
Rob Aitken, ARM

Back to Contents

Call for Papers: The 3rd International Workshop on Bio-Design Automation

The 3rd International Workshop on Bio-Design Automation, June 6 - 7, 2011
San Diego Convention Center, Co-located with the Design Automation Conference

Workshop Website:

The International Workshop on Bio-Design Automation (IWBDA) brings
together researchers from the synthetic biology, systems biology, and
design automation communities. The focus is on concepts,
methodologies, and software tools to enable the computational analysis
of biological systems and the synthesis of biological functions. Still
in its early stages, the field of synthetic biology has been driven by
experimental expertise; much of its success can be attributed to the
skill of the researchers in specific domains of biology. There has
been a concerted effort to assemble repositories of standardized
components. However, creating and integrating synthetic components
remains an ad hoc process. The field has now reached a stage where it
calls for computer-aided design tools. The electronic design
automation (EDA) community has unique expertise to contribute to this
endeavor. This workshop offers a forum for cross-disciplinary
discussion, with the aim of seeding collaboration between the research

Tracks of interest include:
- Design methodologies for synthetic biology.
- Standardization of biological components.
- Automated assembly techniques.
- Computer-aided modeling and abstraction techniques.
- Engineering methods inspired by biology.
- Domain specific languages for synthetic biology.
- Data exchange standards and models for synthetic biology.

The workshop will be held on June 6 - 7, 2011 at the San Diego
Convention Center, co-located with the Design Automation Conference,
the premier conference in the field of electronic design automation
with over 10,000 attendees. Registration information will be posted on
the workshop webpage:

For questions, please email

Abstract Submission

Abstracts should be two pages long, following the ACM SIG Proceedings
templates at Indicate
whether you would like your abstract considered for a poster
presentation, an oral presentation, or both. Include the full names,
affiliations and contact information of all authors.

Abstracts will be reviewed by the Program Committee. Those that are
selected for oral and poster presentations will distributed to
workshop participants and posted on the workshop website.

Abstracts should be submitted by April 5th at:

IWBDA 2011 Collection in PLoS ONE

IWBDA 2011 will have an associated journal special collection in the
interdisciplinary open access journal PLoS ONE. Abstract authors will
be specifically invited and encouraged to submit to this collection,
although submission is open to any paper describing work on IWBDA
tracks of interest. Submitted manuscripts will be reviewed according
to PLoS ONE standard editorial policies.

Key Dates

Call for participation published: January 24th, 2011
Abstract submission deadline: April 5th, 2011
Abstract acceptance notification: May 1st, 2011
Workshop: June 6th & 7th, 2011

Invited Speakers

Adam Arkin, UC Berkeley
Christopher Voigt, UCSF
Erik Winfree, Caltech

Executive Committee

General Chair: Douglas Densmore, Boston University
General Secretary: Leonidas Bleris, UT Dallas
Program Committee Chairs: Xiling Shen, Cornell; Smita Krishnaswamy, Columbia
Publication Chair: Jacob Beal, BBN Technologies
Industry Liaison Chair: Jonathan Babb, MIT
Finance Chair: Natasa Miskov-Zivanov, University of Pittsburgh

Program Committee

J. Christopher Anderson, UC Berkeley; Adam Arkin, UC Berkeley; Jacob
Beal, BBN Technologies; Jonathan Babb, MIT; Leonidas Bleris, UT
Dallas; Kevin Clancy, Invitrogen; Douglas Densmore, Boston University;
Drew Endy, Stanford; Abhishek Garg, Harvard University; Soha Hassoun
Tufts; Mark Horowitz Stanford; Alfonso Jaramillo, Ecole Polytechnique;
Yannis Kaznessis, University of Minnesota; Eric Klavins, University of
Washington; Tanja Kortemme, UCSF; Smita Krishnaswamy, Columbia; Natasa
Miskov-Zivanov, University of Pittsburgh; Kartik Mohanram, Rice; Chris
Myers, University of Utah; Jean Peccoud, Virginia Tech; Andrew
Phillips, Microsoft Research; Mark Riedel, University of Minnesota;
Herbert Sauro University of Washington; Xiling Shen, Cornell; David
Thorsley, University of Washington; Christopher Voigt, UCSF; Ron
Weiss, MIT; Erik Winfree, Caltech; Chris Winstead, Utah State

Back to Contents

Call for Submissions: SIGDA Ph.D. Forum at the Design Automation Conference

Call for Submissions
SIGDA Ph.D. Forum at the Design Automation Conference

The Ph.D. Forum at the Design Automation Conference is a poster
session hosted by SIGDA for Ph.D. students to to present and
discuss their dissertation research with people in the EDA
community. It has become one of the premier forums for
Ph.D. students in design automation to get feedback on their
research and for industry to see academic work in progress: 400 -
500 people attended the last forums. Participation in the forum is
competitive. In 2010, 28 submissions out of 76 were
accepted. Limited funds will be available for travel assistance,
based on financial needs. The forum is open to all members of the
design automation community and is free-of-charge. It is
co-locacted with DAC to attract the large DAC audience, but DAC
registration is not required in order to attend this event.


* Students with at least one published or accepted conference,
symposium or journal paper.
* Students within 1-2 years of dissertation completion and students
who have completed their dissertation during the 2010-2011 academic
* Dissertation topic must be relevant to the DAC community.
* Previous forum presenters are not eligible.
* Students who have presented previously at the DATE and ASP-DAC
Ph.D. forums are eligible, but will be less likely to receive
travel assistance.

Important Dates

* Submission Deadline: Extended Monday, April 11, 2011, 5:00PM MDT
* Notification Date: Monday, May 2, 2011
* Forum Presentation: To be determined

Submission Requirements

* A two-page PDF abstract of the dissertation (in two-column format,
using 10-11 pt. fonts and single-spaced lines), including name,
institution, advisor, contact information, estimated (or actual)
graduation date, whether the work has been presented at ASP-DAC
Ph.D. Forum or DATE Ph.D. Forum, as well as figures, and
bibliography (if applicable). The two-page limit on the abstract
will be strictly enforced: any material beyond the second page
will be truncated before sending to the reviewers. Please include
a description of the supporting paper, including the publication
forum. A list of all papers authored or co-authored by the student,
related to the dissertation topic and included in the two-page
abstract, will strengthen the submission.
* A published (or accepted) paper, in support of the submitted
dissertation abstract. The paper must be related to the
dissertation topic and the publication forum must have a valid ISBN
number. It will be helpful, but is not required, to include your
name and the publication forum on the first page of the paper.
Papers on topics unrelated to the dissertation abstract or not yet
accepted will not be considered during the review process.

Please Note:

* The abstract is the key part of your submission. Write the abstract
for someone familiar with your technical area, but entirely
unfamiliar with your work. Clearly indicate the motivation of your
Ph.D. dissertation topic, the uniqueness of your approach, as
well as the potential impact your approach may have on the topic.
* In the beginning of the abstract, please indicate to which track
your submission belongs to.
* Proper spelling, grammar, and coherent organization are critical:
remember that the two pages may be the only information about
yourself and your PhD research available to the reviewers.
* All submissions must be made electronically through the following


1. System-level Design, Synthesis and Optimization (including
network-on-chip, system-on-chip and multi/many-core, HW/SW
co-design, embedded software issues, modeling and simulation
2. High Level Synthesis, Logic Level Synthesis
3. Physical Design and Manufacturability
4. Power and Reliability Analysis and Optimization (including power
management from system level to circuit level, thermal management,
process variability management)
5. Timing Analysis, Circuit and Interconnect Simulation
6. Signal Integrity and Design Reliability, Analog/Mixed Signals and
7. Verification, Testing, Pre- and Post-Silicon Validation, Failure
8. Reconfigurable and Adaptive Systems
9. Emerging Design and Technologies (carbon nanotubes, molecular
electronics, MEMS, microfluidic system, biologically-inspired
systems, quantum computing, etc.)

Submissions dealing with power modeling, analysis, and/or optimization
may be submitted to any track, depending on the abstraction level and
contents of the work. Same principle also applies to variability-aware
and fault-tolerant design and analysis. Please consult your advisor to
determine which track is the best fit for your submission. If you still
have questions about the most appropriate submission track, you are
encouraged to contact the TPC Chair, Gi-Joon Nam ( or
Gayatri Mehta (

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Call for Papers: The First International IEEE Workshop on Thermal Modeling and Management: Chips to Data Centers

The First International IEEE Workshop on Thermal Modeling and Management: Chips to Data Centers
Call for Papers

High power densities and operating temperatures in multiprocessor
systems impose a number of undesirable effects: performance
degradation, reliability deterioration, high-energy costs, and
physical damage leading to system failures. Recent research has shown
that adverse effects of temperature can be modulated by efficient
thermal monitoring, dynamic thermal management, thermally-aware
architectures, temperature-aware compilation, hybrid computing
fabrics, or by novel cooling technologies. Hardware and software
design and runtime management methods, spanning from chips to
datacenters, play an integral role in the overall thermal behavior and
cooling costs. ITRS projects "Temperature Aware Design" as one of the
cross-cutting design challenges for future manycore systems.

The main goal of this workshop is to provide a forum for the
researchers to share the most recent developments and ideas on thermal
modeling and management in various layers of system design and
management: hardware design, algorithms, applications and software,
operating systems, middleware, and datacenter-level solutions. The
topics of interest include, but are not limited to:

* Thermal Modeling of Manycore / 3D Systems
* Thermal Analysis of Computing and Communication Layers
* Temperature Sensor Placement Algorithms
* Thermally-Aware Design Flows
* Thermal Management at Various Abstractions
* Interconnect / TSV Role in Thermal Optimizations
* Thermal Modeling of Large Scale Distributed Embedded Systems
* Thermally-Aware Distributed Computing
* Context-aware Thermal Management
* Thermal Footprint of Datacenters
* Physically Aware 3D Thermal Management
* Electro-Mechanically Aware Thermal Models
* Network Infrastructures for Enhanced Thermal Management
* Thermally-Aware Embedded Computing Applications
* Co-optimization of Cooling Energy and Computation/ Communication Energy
* Variation Aware Thermal Management in Manycore / 3D Systems
* Thermal Modeling and Management in Emerging Technologies
* Cooling Mechanisms and Technologies in 2-1/2 D, 3D, Hybrid Cores

Submission Guidelines: Prospective authors are invited to submit
papers not exceeding 6 pages (4~6 pages) in length in standard IEEE
two-column format for regular sessions. The IEEE template can be
downloaded at: Prospective
authors should submit an electronic copy of their completed manuscript
through the EasyChair portal
at: Selected
papers from the TEMM workshop will be invited to submit as full-length
papers in the special edition for Journal of Sustainable Computing:

The submission and acceptance timeline is given below.

Paper submission date: April 25 2011

Notification date: May 25 2011

Camera Ready papers: June 6 2011

Registration: All participants will be required to register for the
IGCC'11 conference ( The registration
includes access to the workshop. For any questions related to the
workshop, please

Workshop Co-Chairs:
Dhireesha Kudithipudi, Rochester Institute of Technology, USA
Qinru Qiu, Binghamton University, USA
Ayse Kivilcim Coskun, Boston University, USA

Publicity Chair:
Sherief Reda, Brown University, USA

Technical Program Committee:
David Atienza, EPFL, Switzerland
Jose Ayala, Compultense Univ. of Madrid, Spain
Tianzhou Chen, Zhejiang University, China
Siddharth Garg, University of Waterloo, Canada
Kartik Gopalan, Binghamton University, USA
Omer Khan, MIT, USA
Eren Kursun, IBM T.J. Watson Research Center, USA
Byeong Lee, Univ. of Texas San Antonio, USA
Gang Quan, Florida International University, USAÊ
Emre Salman, Stony Brook University, USA
Mircea Stan, University of Virginia, USA

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Call for Submissions: Second ACM Student Research Competition at the ACM/IEEE Design Automation Conference

Second ACM Student Research Competition at the ACM/IEEE Design Automation Conference

The ACM Special Interest Group on Design Automation is organizing an
ACM Student Research Competition for undergraduate and graduate
students in conjunction with the Design Automation Conference. Authors
of accepted submissions will get travel grants from ACM/Microsoft to
attend the event at DAC. The event consists of several rounds, as
described at and, where you can also find more
details on student eligibility and timeline.

Details on abstract submission

Research projects from all areas of design automation/electronic
design are encouraged. The author submitting an extended abstract must
still be a student at the time of submission. Each submission should
be made as a single PDF file at . Please
include the author's name, affiliation, postal address, and email
address; research advisor's name; ACM student member number; category
(undergraduate or graduate); research title; and an extended abstract
(maximum 2 pages or 800 words) containing the following sections:

* Problem and Motivation: This section should clearly state the
problem being addressed and explain the reasons for seeking a
solution to this problem.
* Background and Related Work: This section should describe the
specialized (but pertinent) background necessary to appreciate the
work. Include references to the literature where appropriate, and
briefly explain where your work departs from that done by
others. Reference lists do not count towards the limit on the length
of the abstract.
* Approach and Uniqueness: This section should describe your approach
in attacking the problem and should clearly state how your approach
is novel.
* Results and Contributions: This section should clearly show how the
results of your work contribute to design automation/electronic
design and should explain the significance of those results.

Prior to uploading the PDF file, you will be asked to submit a
separate short abstract (maximum of 100 words) for possible
publication in the conference proceedings that serves as a succinct
description of the project.

Important dates
Abstract submission deadline: April 8, 2011
Acceptance notification: May 1, 2011
Poster session at DAC: June 7, 2011
Presentation session at DAC: June 8, 2011
Award winners announced at DAC: June 9, 2011
Grand Finals winners honored at ACM Awards Banquet: June 2012

Naehyuck Chang (, Seoul National University
Srinivas Katkoori (, University of South Florida

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Call for Papers: Journal of ECE Special Issue on ESL Design Methodology

Journal of Electrical and Computer Engineering
Special Issue on ESL Design Methodology

ESL (electronic system-level) design is an emerging design methodology
that allows designers to work at higher levels of abstraction than
typically supported by register transfer level (RTL) descriptions. Its
growth has been driven by the continuing complexity of IC design, the
shortening time to market and growing number of design constraints and
objectives, which have made RTL implementation less efficient.

ESL methodology holds the promise of dramatically improving design
productivity by accepting designs written in high-level languages such
as C, SystemC, C++, and MATLAB, etc. and implementing the function
straight into hardware. Designers can also leverage ESL to optimize
performance and power by converting compute intensive functions into
customized cores in SoC designs or FPGAs. It can also support early
embedded-software development, architectural modeling, and functional

ESL has been predicted to grow in both user base and revenue steadily
in the coming decade. Meanwhile, the design challenges in ESL
remain. Some important research challenges include effective
hardware/software partitioning and co-design, high-quality high-level
synthesis, seamless system IP integration, accurate and fast
performance/power modeling, and efficient debugging and verification,
etc. Research topics of interest for this special issue include, but
are not limited to:

* New algorithmic development for high-level synthesis
* Domain-specific high-level synthesis (DSP, processor-based, control-intensive, etc.)
* High-level synthesis for emerging technologies (3D, biochips, nanoscale circuits, etc.)
* Extensible/reconfigurable processor synthesis
* ESL design space exploration
* Virtual prototyping
* Transaction Level Modeling
* Hardware/software partitioning and co-design
* Hardware/software interaction and interface
* ESL-to-RTL verification
* ESL debugging
* ESL power/performance analysis
* ESL-IP integration
* ESL for FPGAs
* ESL and embedded-software development
* Design case studies with ESL

Before submission authors should carefully read over the journal's
Author Guidelines, which are located at Prospective
authors should submit an electronic copy of their complete manuscript
through the Journal Manuscript Tracking System at according to the following timetable:

Manuscript Due: July 1, 2011
First Round of Reviews: October 1, 2011
Publication Date: January 1, 2012

Lead Guest Editor:
Deming Chen, University of Illinois at Urbana-Champaign, USA

Guest Editors:
Kiyoung Choi, Seoul National University, Korea
Philippe Coussy, Lab-STICC, Université de Bretagne-Sud, France
Yuan Xie, Pennsylvania State University at University Park, USA
Zhiru Zhang, Xilinx Inc., USA

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Call for Participation: 1st CRA-W/CDC Workshop on Diversity in Design Automation and Test

1st CRA-W/CDC Workshop on Diversity in Design Automation and Test:
Putting D(iversity) in Design Automation and Test (WD2AT)
Pittsburgh, PA
May 23-24, 2011

The focus of this workshop is on design automation and test (DA&T),
the field of of computing targeting the development of software tools
for designing and testing electronic systems. The workshop is intended
to provide senior undergraduate students, graduate students, and early
post-doctoral researchers from underrepresented groups (women and
minority) an overview of the field, research directions, and career
paths in DA&T. Funding is available to help cover travel costs and
subsistence (hotel, food) during the workshop for attendees.

The application deadline for interested attendees is April 18, 2011.
Selected participants will be notified by April 29, 2011.
Applications should be sent via email to Diana Marculescu
( Please fill in all fields of this spreadsheet
( and
send it via email to the email address above along with: (i) A
one-page statement on what do you expect to get from and contribute to
this workshop; and (ii) A one-page description of a research poster,
if you would like to present one (in that case, make sure you mark the
corresponding field in the spreadsheet).

Application deadline: Monday, April 18, 2011
Notification of acceptance: Friday, April 29, 2011

Diana Marculescu, Carnegie Mellon University,
Shawn Blanton, Carnegie Mellon University,
Jun Yang, University of Pittsburgh,
Natasa Miskov-Zivanov, University of Pittsburgh,
Alex Jones, University of Pittsburgh,

The workshop is part of a series of Discipline-specific Mentoring
Workshops organized by Computing Research Association's Committee on
the Status of Women in Computing and the Coalition to Diversify
Computing (CDC). Additional support for this workshop comes from:
Carnegie Mellon University (Dept. of ECE, Office of Vice Provost for
Education, Offices of Assist. Vice Provosts for Undergraduate and
Graduate Education), University of Pittsburgh (Swanson School of
Engineering), ACM Special Interest Group on Design Automation, IEEE
Council on Electronic Design Automation, Semiconductor Research
Corporation/Education Alliance, Synopsys, and Texas Instruments.

Back to Contents

Call for Papers: 19th IFIP/IEEE International Conference on Very Large Scale Integration

19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2011)
October 3-5, 2011
Hong Kong, China

VLSI-SoC 2011 is the 19th in a series of international conferences
sponsored by IFIP TC 10 Working Group 10.5, IEEE CEDA and CASS that
explores the state-of-the-art and the new developments in the field of
Very Large Scale Integration (VLSI), System-on-Chip (SoC) and their
designs. Past Conferences have taken place in Edinburgh, Trondheim,
Tokyo, Vancouver, Munich, Grenoble, Gramado, Lisbon, Montpellier,
Darmstadt, Perth, Nice, Atlanta, Rhodes, Florianópolis and Madrid. The
purpose of VLSI-SoC is to provide a forum to exchange ideas, and show
industrial and research results in the fields of VLSI/ ULSI Systems,
SoC design, VLSI CAD and Microelectronic Design and Test. This edition
special emphasis is given to the research area of “SoC design for
ubiquitous sensing and computing”.

Topics of interest include but are not limited to:
* Analog and Mixed-Signal IC Design
* Circuits and Systems for Micro-sensing Applications
* 3-D Integration, Physical Design, Compact Modelling, and
Electromagnetic Analysis
* Design for Variability, Reliability, Fault Tolerance, Test
* Digital Signal Processing and Image Processing IC Design
* New Devices, MEMS and Microsystems
* Prototyping, Validation, Verification, Modelling and Simulation
* System-On-Chip Design, Digital Architectures
* Embedded Systems Design and Real-Time Systems
* Reconfigurable Systems, Compilers
* Logic and High-Level Synthesis
* Low-Power and Thermal-aware Design

Important Deadlines:
Paper Submission: EXTENDED April 14, 2011, 12:00 noon GMT.
Special Session Proposal: April 4, 2011
Notification of acceptance: June 17, 2011
Camera-ready: July 11, 2011

Paper Submission:
Papers should present original research results not published or
submitted for publication in other forums. Papers should not exceed 6
pages (single-spaced, 2 columns, 10pt font). Electronic submission in
PDF format to the website is required. The
proceedings will be published by IEEE and available through IEEE
Xplore. They will be distributed during the conference to all
participants. A selection of the conference best papers will be
invited to submit an extended version to be included as chapters of a
book to be published by Springer. Author and contact information
(name, street/ mailing address, telephone, fax, e-mail) must be
entered during the submission process.

Paper Format:
Submissions should be in camera-ready two-column format, following
the IEEE proceedings specifications located at:

Paper Publication and Presenter Registration:
Papers will be accepted for regular or poster presentation at the
conference. Every accepted paper MUST have at least one author
registered to the conference by the time the camera ready paper is
submitted. The author is also expected to attend the conference and
present the paper.

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Notice to Authors

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