SIGDA E-News 1 June 2012, Vol. 42, No. 6

1 June 2012 :: ACM/SIGDA E-NEWSLETTER :: Vol. 42, No. 6
 Special Interest Group on Design Automation
1 June 2012, Vol. 42, No. 6
Online archive:
1. SIGDA News
    From: Matthew Guthaus <>
    From: Sudeep Pasricha <>
    From: Lin Yuan <>

2. What is Reversible Computing?
    Contributing author: Himanshu Thapliyal <>
    From: Srinivas Katkoori <>

3. Paper Submission Deadlines
    From: Debjit Sinha <>

4. Upcoming Conferences and Symposia
    From: Debjit Sinha <>

5. Upcoming Funding Opportunities
    From: Sudeep Pasricha <>

6. Call for Papers: International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)
    From: Philip Brisk <>

7. Call for Papers: International Conference on VLSI Design and International Conference on Embedded Systems
    From: Sachin S. Sapatnekar <>

8. Call for participation: 2012 CAD Contest
    From: Zhuo Li <>

9. Call for Abstracts: VLSI-SoC 2012 PhD Forum
    From: Matthew Guthaus <>

10. Call for Papers: International High-Level Design, Validation and Test Workshop (HLDVT)
    From: Hiren D. Patel <>

11. Call for Papers: Work in Progress Session @ International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
    From: Sudeep Pasricha <>
Comments from the Editors

Dear ACM/SIGDA members,

After nearly 6 years as (Co-)Editor of the ACM SIGDA E-Newsletter,
Matthew Guthaus will be stepping down after this month.
Sudeep Pasricha, Assistant Professor at Colorado State University, will
be assuming these duties as of this issue. Sudeep has been an Associate
Editor of the E-Newsletter for well over a year. Please modify your spam
filter settings to allow email from in order to not
miss any future E-Newsletters.

In this issue, we have a very interesting article on Reversible
Computing. If you are interested in contributing to this column in
the future, please contact Srinivas Katkoori <>.
An article only needs to be about 1 page long with several references.
All articles are included in the ACM digital library and there is no
restriction for the reproduction of the article for printed
publication later.

Matthew Guthaus, E-Newsletter Editor;
Sudeep Pasricha, E-Newsletter Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Srinivas Katkoori, E-Newsletter Associate Editor

Back to Contents


"A Facebook Phone Could Set Up A Google Battle",2817,2404947,00.asp
First Opera, now a smartphone ... next, you'll read a story about how Facebook's
considering buying a television manufacturer so that everyone can enjoy social
updates and sitcoms via the "FB TV."

"Understanding wireless charging configurations"
The increasing popularity of battery-powered consumer electronic devices such as portable
media players, smartphones, and tablets has led to a host of different chargers and a tangle
of wires littering the home.

"HP cuts data center power in lab tests"
Engineers at HP Labs claim they have demonstrated software in a research setting that
significantly lowers power consumption for large data centers. The company will test the
tools in a full production data center at Hewlett-Packard and work on turning them into
products that could ship with HP's container-class systems.

"Software, the last frontier for ultra-low-power microcontroller performance"
The microcontroller industry has been aggressively focused on ultra-low-power silicon,
enabling applications that outlive the typical shelf life of many batteries. As vendors push
technologies and skip process nodes, gone are the days of milliamps. Microcontrollers
have entered a world of microamps and nanoamps thanks to innovative use of lower-
power standby modes, intelligent analog peripherals, power gating, and other silicon a

"Design for reliability - the golden age of simulation driven product design"
The design and implementation process for integrated circuits (ICs) has been honed
and perfected for decades by the design and the electronic design automation (EDA)
community. However, the reliability verification process has been slow to catch up,
especially due to the complex nature of failure mechanisms. Chip designers in the
past were willing to take risks when it came to reliability verification because it was
not seen as a functional failure or something that caused yield fallout. But times
have changed and the EDA and simulation software community has swiftly responded
to the needs of a simulation driven reliability analysis model. This article will delve
into what it takes to design for reliability today.

"Renesas cuts 14,000 jobs; fab sale to TSMC"
Renesas Electronics Corp. plans to eliminate up to 14,000 jobs, while selling the company's
leading system-chip fab in Yamagata to Taiwan Semiconductor Manufacturing Co., according
to a report in Nikkei, Japan's economic newspaper.

"Intel to spend $40 million on international university research"
Intel Corp. said Thursday (May 24) it plans to plough more than $40 million into a worldwide
network of university research centers over the next five years in an international counterpart
to the company's U.S.-based Intel Science and Technology Centers program (ISTCs).

"UMC breaks ground for $8-billion fab expansion"
Foundry chip company United Microelectronics Corp. has held a ground breaking ceremony for
Phases 5 and 6 (P5 and P6) of its Fab 12A 300-mm wafer fab complex at Tainan, Taiwan.
The expansion is intended to provide manufacturing capacity to extend the company's 28-nm
production and to provide the basis for 20-nm and 14-nm production and will ultimately cost
nearly $8 billion, the company said.

"Report reveals fake chips in U.S. military hardware"
More than a million suspect counterfeit electronic components have been used in 1,800 separate
cases of bogus parts affecting U.S. military hardware, according to a report produced by the
Senate Armed Services Committee. The instances affect a number of military airplanes, helicopters,
missile and electronic warfare systems. The year-long investigation found large numbers of
counterfeit parts - mainly from China - have been making their way into critical defense systems.
A 112-report produced by the committee highlights cases in the U.S. Air Force's largest cargo
plane and in assemblies intended to go in special operations helicopters and U.S. Navy
surveillance planes.

"Handset shipments projected to rise 11% in 2012"
Sales of smartphones continues to drive mobile device market growth in the first quarter of 2012,
but global sales of all cell phones declined compared to the first quarter of 2011, according to
market research firm Forward Concepts Inc. Sales of all handsets came to about 379 million units
worldwide in the first quarter, down 9 percent from the first quarter of 2011, Forward Concepts said.

"Hybridization of processors increasingly rapidly, says report"
Hybrid processors with two or more different types of processor cores accounted for half of the
$111 billion processor market in 2011, according to a new report by market research firm IMS
Research. According to the report, hybridization of processors appears to be a critical step
in upping the competitive edge in computers and is also a step for chip vendors into smartphones,
tablets and other high performance embedded devices. Hybrid applications processor growth in
smartphones is projected to grow at a compound annual growth rate (CAGR) of 10 percent through
2016 and at a 14 percent CAGR in tablets, according to IMS.

"Synopsys Acquires RSoft Design Group"
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification
and manufacture of electronic components and systems, today announced it has completed the
acquisition of privately held RSoft Design Group, Inc. (RSoft), a leading provider of photonics
design and simulation software headquartered in Ossining, New York.

"Xilinx Ships World's First Heterogeneous 3D FPGA"
Xilinx Inc., (NASDAQ: XLNX) today announced initial shipments of the Virtex-7 H580T FPGA, the
world's first 3D heterogeneous all programmable product. Virtex-7 HT devices use Xilinx's stacked
silicon interconnect (SSI) technology to deliver the industry's highest bandwidth FPGAs, featuring
up to sixteen 28 Gbps and seventy-two 13.1 Gbps transceivers, making them the only single-chip
solutions for addressing key Nx100G and 400G line card applications and functions.

Back to Contents

What is Reversible Computing?

Himanshu Thapliyal, University of South Florida, Tampa

Reversible computing appears to be promising due to its wide applications
in emerging technologies such as quantum computing, quantum dot cellular
automata, optical computing, ultra-low-power nanocomputing, etc [1]. Reversible
computing is based on logic circuits that can generate unique output vector
from each input vector, and vice versa, that is, there is a one-to-one
mapping between the input and the output vectors. Hence, reversible circuits
do not lose information during computation and are built from reversible
logic gates. Classical logic gates are irreversible since input vector
states cannot be uniquely reconstructed from the output vector states.
As an example, considering conventional irreversible 2 inputs XOR with
inputs (A, B) which are mapped to output (Q=A XOR B), a unique input vector
cannot be constructed from the output vector in this case. This is because
for output Q=0, there are two input vectors AB = (00, 11) that give rise to
it. Now, considering a reversible XOR gate which is a 2 inputs, 2 outputs
reversible gate with inputs (A, B) which are mapped to outputs (P=A , Q=A XOR B),
it is evident that a unique input vector can be constructed for every output vector.

As a fundamental contribution in [2], Landauer has shown that during
irreversible computation 1 bit of information lost results in KTln2
Joules of energy dissipation. Bennett in another seminal contribution [3],
proved that this KTln2 joules of energy dissipation will not occur if
computation is performed in a reversible manner. Thus, reversible logic
can be useful to design non-dissipative circuits if the implementation
platform is also physically reversible. CMOS cannot be considered as a
practical implementation platform as CMOS is not physically reversible.
Reversible computing can find promising applications in emerging nano-
technologies such as Quantum Dot Cellular automata (QCA) computing, Optical
Computing, and Superconductor Flux Logic (SFL) family, etc., where the
energy dissipated due to information destruction will be a significant
factor of the overall heat dissipation of the system. Thus, one of the
primary motivations for adopting reversible logic lies in the fact that
it can provide a logic design methodology for designing ultra-low-power
circuits beyond KTln2 limit for those emerging nanotechnologies in which
the energy dissipated due to information destruction will be a significant
factor of the overall heat dissipation [4].

Reversible logic has major application in quantum computing. Quantum computer
is considered one of the most promising computing paradigm in which
computation can be performed at an atomic level. Thus, provide a medium
to work beyond the existing limits of the semiconductor industry. A
quantum computer performs an elementary unitary operation on one, two or
more two-state quantum systems called qubits. Any unitary operation is
reversible and hence quantum networks must be built from reversible logic
gates [5]. Thus, the feasibility of reversible logic gates could critically
impact the realization of quantum computing. Further, in CMOS based circuits
reversible logic can potentially recover and retain a fraction of the signal
energy that can be reused for subsequent operations by doing the computation
using the forward path and then undoing the computation using the backward
path. These concepts have been implemented in CMOS to save significant amount
of energy dissipation using the concepts such as reversible energy recovery
logic (RERL) etc [6].

Also, reversible logic has promising applications in online and offline
testing of faults. Reversible circuits can greatly reduce the overall
manufacturing cost by reducing the cost involved in testing. For example,
in reversible logic based sequential circuits, unidirectional stuck-at faults
as well as single/missing additional cell defect can be detected by using
only two test vectors, all 0s and all 1s, thereby eliminating the need for
any type of scan-path access to internal memory cells [7, 8].

There are number of implementation platforms that are being explored for
physical implementation of reversible gates. At present it is not sure which
implementation technology will be the future of the reversible computers.
Thus, there is a need of technology independent design and synthesis of
reversible logic circuits. Further, as nanoelectronic devices tend to have
high permanent and transient faults and are susceptible to high error rates,
reversible logic can be of interest to the researchers in reducing the number
of test patterns for fault detection in nanocircuits. Finally, as reversible
circuits are dissipation less in nature, logic circuits based on reversible
logic can be the future of ultra-low-power nanocircuits such as bio-implantable

[1] S.K.Moore,"Computing's power limit demonstrated", IEEE Spectrum, vol.48,
no. 5, pp. 14-16, May 2012

[2]R. Landauer, “Irreversibility and heat generation in the computational
process,” IBM J. Res. Dev., vol. 5, pp. 183-191, 1961.

[3] C. H. Bennett, “Logical reversibility of computation,” IBM J. Res. Dev.,
vol. 17, pp. 525–532, Nov. 1973

[4] J. Ren and V. K. Semenov, “ Progress with physically and logically reversible
superconducting digital circuits,” IEEE Trans. on Applied Superconductivity,
vol. 21, no.3, pp. 780-786, June 2011.

[5] V.Vedral, A. Barenco, and A. Ekert, “Quantum networks for elementary
arithmetic operations,” Phys. Rev. A, vol.54, no. 1, pp.147-153, Jul 1996.

[6] J. Lim, D.-G. Kim, and S.-I. Chae, “nmos reversible energy recovery logic
for ultra-low energy applications,” IEEE Journal of Solid-State Circuits, vol.35,
no.9, pp. 865-875, June 2000.

[7] H. Thapliyal and N. Ranganathan, “Design of testable reversible sequential
circuits,” to appear IEEE Trans. on VLSI Systems, 2012.

[8] H. Thapliyal, “Design, synthesis and test of reversible logic circuits
for emerging nanotechnologies,” Ph.D. Dissertation, Univ. of South Florida,
Tampa, 2011

Back to Contents

Paper Submission Deadlines

MICRO'12 - Int'l Symposium on Microarchitecture
Vancouver, Canada
Deadline: Jun 8, 2012 (Abstracts due: Jun 1, 2012)
Dec 1-5, 2012

ICFPT'12 - Int'l Conference on Field-Programmable Technology
Seoul, Korea
Deadline: Jun 8, 2012
Dec 10-12, 2012

ICPADS'12 - Int'l Conference on Parallel and Distributed Systems
Singapore, Singapore
Deadline: Jun 15, 2012
Dec 17-19, 2012

HLDVT'12 - Int'l High-Level Design, Validation and Test Workshop
Huntington Beach, CA
Deadline: Jun 17, 2012
Nov 9-10, 2012

ISED'12 - Int'l Symposium on Electronic System Design
Kolkata, India
Deadline: Jun 17, 2012
Dec 19-22, 2012

HiPEAC'13: Int'l Conference on High Performance Embedded Architectures & Compilers
Berlin, Germany
Deadline: Jun 18, 2012
Jan 21-23, 2013 hipeac2013

BIOCAS'12 - Biomedical Circuits and Systems Conference
Hsinchu, Taiwan
Deadline: Jun 30, 2012
Nov 28-30, 2012

VLSI-SoC'12 - Int'l Conference on Very Large Scale Integration and System on Chip PhD Forum
Santa Cruz, CA
Deadline: Jul 1, 2012
Oct 7-12, 2012

ASP-DAC'13 - Asia and South Pacific Design Automation Conference
Yokohama, Japan
Deadline: Jul 13, 2012
Jan 22-25, 2013

ISSCC'13 - Int'l Solid-State Circuits Conference
San Francisco, CA
Deadline: Sep 10, 2012
Feb 17-21, 2012

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Upcoming Conferences and Symposia

DAC'12 - Design Automation Conference
San Fransisco, CA
Jun 3-7, 2012

SLIP'12 - System Level Interconnect Prediction
(co-located with DAC'12)
San Francisco, CA
June 3, 2012

DFM&Y'12 - Int'l Workshop on Design for Manufacturability & Yield
San Francisco, CA (Co-located with DAC'12)
Jun 4, 2012

IWBDA'12 - Int'l Workshop on Bio-Design Automation
San Francisco, CA (Co-located with DAC'12)
Jun 4-5, 2012

ISCA'12 - Int'l Symposium Computer Architecture
Portland, OR
Jun 9-13, 2012

AHS'12 - NASA/ESA Conference on Adaptive Hardware and Systems
Nuremburg, Germany
Jun 25-28, 2012

ASQED'12 - Asia Symposium on Quality Electronic Design
Kuala Lumpur, Malaysia
Jul 10-12, 2012

MEMOCODE'12 - Int'l Conference on Formal Methods and Models for Codesign
Arlington, VA
Jul 16-18, 2012

PACT'12 - Int'l Conference on Parallel Architectures and Compilation
Minneapolis, MN
Sep 21-25, 2012

BodyNets'12 - Int'l Conference on Body Area Networks
Oslo, Norway
Sep 24-26, 2012

VLSI-SoC'12 - Int'l Conference on Very Large Scale Integration and System on Chip
Santa Cruz, CA
Oct 7-12, 2012

ESWEEK'12 - Embedded Systems Week (CASES, CODES+ISSS, and EMSOFT)
Tampere, Finland
Oct 7-12, 2012

Wireless Health'12
San Diego, CA
Oct 22-25, 2012

ICCAD'12 - Int'l Conference on Computer-Aided Design
San Jose, CA
Nov 5-8 2012

HiPC'12 - Int'l Conference on High Performance Computing
Pune, India
Dec 18-21, 2012

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Upcoming Funding Opportunities


Office of Naval Research (ONR) Sabbatical Leave Program
Deadline: N/A

Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Deadline: Continuous


Microsystems Technology Office-Wide Broad Agency - DARPA-BAA-10-35
Deadline: September 1, 2012


Robust Computational Intelligence - AFOSR-BAA-2011-01
Deadline: Continuous

Systems and Software - AFOSR-BAA-2011-01
Deadline: Continuous

ERDC BAA - Computational Science and Engineering (ITL-1)
Deadline: Continuous

Advanced Distributed Sensor Technologies - BAA 57-09-06
Deadline: Continuous

Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
Deadline: Continuous

High Performance Computing on Massively Parallel Architectures (BAA 64-09-01)
Deadline: Continuous

ASEE-NRL Postdoctoral Fellowship Program
Deadline: N/A


Postdoctoral Appointments
Deadline: N/A

Sabbaticals and Faculty Appointments
Deadline: continuous

McDonnell Foundation

Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Deadline: continuous


Core Techniques and Technologies for Advancing Big Data Science & Engineering (BIGDATA)
Deadline: June 13, 2012

Research Coordination Networks
Deadline: June 15, 2012

Industry/University Cooperative Research Centers Program (I/UCRC)
Deadline: June 29, 2012

Cyberlearning: Transforming Education (Cyberlearning)
Deadline: July 16, 2012

Faculty Early Career Development (CAREER) Program
Deadline: July 23-25, 2012

Failure-resistant systems (FRS)
Deadline: July 26, 2012


Call for Grant Applications in Cross-disciplinary Semiconductor Research (CSR)
Deadline: June 4, 2012

Focus Center Research Program
Deadline (White Paper): June 15, 2012

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Call for Papers: International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)


HiPEAC 2013: 8th International Conference on High-Performance and
Embedded Architectures and Compilers

January 21-23, 2013, Berlin, GERMANY

* Workshops/tutorials: June 1, 2012
* Papers: June 18, 2012
* Paper selection: November 15, 2012
* Posters: October 15, 2012

The HiPEAC conference is the premier scientific networking forum for
experts in computer architecture, programming models, compilers and
operating systems for embedded and general-purpose systems. Emphasis
is given on cross-cutting research and innovative ideas (new
programming models, novel architecture approaches, new technologies,
etc.). The conference hosts a number of associated workshops,
tutorials, a large poster session and an exhibition that run in
parallel with the conference. The 8th HiPEAC conference will take
place in Berlin, Germany from Monday 21 to Wednesday January 23, 2013.


In 2011, TACO and HiPEAC jointly carried out an experiment with a
publication model where original contributions on HiPEAC topics were
solicited for TACO. Record-high numbers of submitted and accepted
papers witness the significant interest in this model. This year, TACO
seeks original submissions at any time. Accepted TACO papers by
November 15, 2012 and whose topics match those of HiPEAC will be
selected and invited for presentation at HiPEAC conference. In order
to enjoy two rounds of review, and to be considered for invitation to
present at the HiPEAC 2013 conference, papers should be submitted no
later than June 18, 2012. Accepted papers will be published in
regular issues of ACM TACO.

For submission details, please refer to

Topics of interest to HiPEAC 2013 include, but are not limited to:

- Processor architectures
- Memory system optimization
- Power, performance and implementation efficient designs
- Reliability and real-time support in processors, compilers and
run-time systems
- Network and security processors
- Application-specific processors and accelerators
- Reconfigurable architectures
- Simulation and methodology
- Hardware and run-time support for programming languages
- Compiler techniques
- Feedback-directed optimization
- Program characterization and analysis techniques
- Dynamic compilation, adaptive execution, and continuous
- Binary translation/optimization
- Code size/memory footprint optimizations


HiPEAC 2013 General Chairs:
* Ben Juurlink (Technische Universitat Berlin, Germany)
* Keshav Pingali (University of Texas Austin, USA)

Program Chairs:
* Andre Seznec (INRIA/IRISA, France)
* Lawrence Rauchwerger (Texas A&M University, USA)

Editor-in-chief of ACM Transactions on Architecture and Code Optimization:
* Tom Conte (Georgia Institute of Technology, USA)

Poster Chairs:
* Koen De Bosschere (Ghent University, Belgium)
* Qing Yi (University of San Antonio, USA)

Workshops/Tutorials Chair:
* Sascha Uhrig (Technische Universitat Dortmund, Germany)

Industrial exhibit and European projects sub-committee:
* Henri-Pierre Charles (French Alternative Energies and Atomic Energy
Commission, France)
* Rosa M. Badia (Barcelona Supercomputing Center, Spain)

Publicity Chairs:
* Philip Brisk (U.C Riverside, USA)
* Nikola Puzovic (Barcelona Supercomputing Center, Spain)

Finance Chair:
* Jeroen Borghs (Ghent University, Belgium)

Submission Chair:
* Michiel Ronsse (Ghent University, Belgium)

Web and Registrations Chair:
* Klaas Millet (Ghent University, Belgium)

Local organizing committee:
* Nico Moser (Technische Universitat Berlin, Germany)
* Paula Herber (Technische Universitat Berlin, Germany)
* Reinier van Kampenhout (Fraunhofer FIRST, Germany)

Steering Committee:
* Anant Agarwal (MIT, USA)
* Koen De Bosschere (Ghent University, Belgium)
* Albert Cohen (INRIA, France)
* Tom Conte (Georgia Institute of Technology, USA)
* Wen-mei W. Hwu (UIUC, USA)
* Walid Najjar (UC Riverside, USA)
* Per Stenstrom (Chalmers University, Sweden, Chair)
* Theo Ungerer (University of Augsburg, Germany)
* Mateo Valero (UPC, Spain)

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Call for Papers: International Conference on VLSI Design and International Conference on Embedded Systems


January 5-9, 2013
Pune, India

THEME: Green Technologies - A New Era for Electronics

Submissions (Paper/Tutorial/Special Sessions): July 2, 2012
Acceptance of notification: September 7, 2012
Camera ready paper due: October 1, 2012

This joint conference is a forum for researchers and designers to
present and discuss current topics in VLSI design, electronic design
automation, embedded systems, and enabling technologies. Two days of
tutorials will be followed by three days of regular paper sessions,
special sessions, and embedded tutorials. Industry presentation
sessions along with exhibits, panel discussions, Design Contest, and
Education Forum round off the program. The theme for the conference is
"Green Technologies - A New Era for Electronics," which explores the
ability of VLSI and embedded circuits and systems to positively impact
the environment. Example areas under the theme include (but are not
restricted to) designing energy-efficient VLSI circuits, improving the
efficiency of energy-hungry applications such as data centers,
developing intelligent monitoring and control systems such as smart
grids, and using integrated circuits or embedded systems to leverage
novel green technologies.

TOPICS OF INTEREST: Papers are invited on previously unpublished results
in various categories related to VLSI design, electronic design,
embedded systems, and enabling technologies. For details, please refer
to the conference website.

relevance to this conference should be submitted as two-page abstracts.
On acceptance, authors are required to submit full regular papers.

HALF-DAY AND FULL-DAY TUTORIALS: Continuing a tradition of running a
highly successful series of tutorials, the first two days of the
conference will be dedicated to tutorials on recent topics in VLSI
design, EDA, VLSI technology, and embedded systems. Tutorial proposals
should be submitted through the conference website by July 2, 2012.

PANELS: Proposals must be submitted with an abstract, and a list of

SUBMISSIONS: All submissions should be made electronically via the
conference website by July 2, 2012. Your manuscript should clearly state
the novel ideas, results and applications of the contribution. Paper
submissions will undergo a double-blind review. Papers must be in PDF
format and not exceed 6 single-spaced pages including figures and
references in two-column IEEE conference paper format. Papers exceeding
the 6 page limit or identifying the authors will be rejected without
review. All submissions of papers and proposals will imply that, if
selected, they will be presented at the conference in person. Hence,
approvals from parent organizations must be obtained before the
submissions are made.


Technical Program Co-chairs:
Alok Jain ( and Sachin Sapatnekar (

Nagi Naganathan (

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Call for participation: 2012 CAD Contest

Call for participation

The annual CAD Contest in Taiwan, sponsored by the Ministry of Education
(MOE), has been held for 12 consecutive years and has successfully boosted
the EDA research momentum in Taiwan. In 2012, we continue this great
tradition and internationalize it under the joint sponsorship of IEEE CEDA
and Taiwan MOE. The new contest, 2012 CAD Contest at ICCAD, is open
worldwide to have more significant contributions to our global EDA
community. You are invited to participate!


In the first year (2012), we design three contest problems covering three
distinct areas:

1. Finding the minimal logic difference for functional ECO contributed by
Taiwan Cadence Design Systems, Inc.
2. Design hierarchy aware routability-driven placement contributed by IBM
3. Fuzzy pattern matching for physical verification contributed by Mentor
Graphics Corp.


1. The contestants should be university students.
2. Contestants must register by August 1, 2012.
3. Changes of team members, advisors or topics should be made by the
deadline of registration.

Evaluation and ranking

1. Each topic is ranked separately.
2. The quality metrics are determined by the problem specifications,
including correctness, runtime and memory usage.
3. Each submitted program will be evaluated by the announced benchmarks and
hidden benchmarks.
4. The officially supported programming language will be C/C++. For other
languages, please check with the contest organizers first. MATLAB is
prohibited for use in the contest.
5. The library that can be used in the contest is the standard C/C++

6. System specification:

Linux version: TBD
Gcc version: TBD
GNU libc version: TBD

Tentative Contest Schedule

1. Call for participation April 25, 2012.
2. Official website open April 25, 2012
3. Problem description announcement April 25, 2012
4. Registration deadline August 1, 2012
5. Alpha submission August 8, 2012
6. Submission deadline September 24, 2012
7. Final announcements November 2012 (at ICCAD)

Other Information

1. For any other inquiries, please send emails
2. Please add "ICCAD2012_Contest" to the subject line for any emails
regarding the contest.
3. Any update will be announced on contest website:
4. There may be a special session organized for the contest at ICCAD 2012
(we will be notified by the end of May). This session includes three
presentations from the contest organizers for the three contest problems and
the award ceremony.


1. Contest chair:
Yih-Lang Li (National Chiao Tung University, Taiwan)
2. Co-chairs:
Iris Hui-Ru Jiang (National Chiao Tung University, Taiwan)
Zhuo Li (IBM, Corp.)
3. Topic chairs:
Jane Wang (Taiwan Cadence Design Systems, Inc.)
Natarajan Viswanathan (IBM Corp.)
Andres Torres (Mentor Graphics Corp.)


1. IEEE CEDA (Technical sponsorship)
2. Taiwan Ministry of Education (Financial sponsorship)

Back to Contents

Call for Abstracts: VLSI-SoC 2012 PhD Forum

Call for Abstracts

at the

20th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
October 7-10, 2012
Santa Cruz, CA, USA
Dream Inn Hotel

VLSI-SoC 2012 is the 20th in a series of international conferences
sponsored by IFIP TC 10 Working Group 10.5, IEEE CEDA and IEEE CASS
that explores the state-of-the-art and the new developments in the
field of Very Large Scale Integration (VLSI) and System-on-Chip
(SoC). VLSI-SoC 2012's Ph.D. Forum is a poster session dedicated to
the exchange of ideas and experiences of Ph.D. students from different
parts of the world. Elected Ph.D. students have an opportunity to
discuss their thesis and research work with specialists with the
community. This exchange offers a good opportunity for students to
receive valuable feedback and gain exposure in the job
market. Furthermore, this forum also provides a great chance for
industry officials to meet junior researchers, giving an avenue for
incorporating the latest research developments into their companies.

Topics of interest include but are not limited to:
* Analog and Mixed-Signal IC Design
* Circuits and Systems for Micro-sensing Applications
* 3-D Integration, Physical Design, Compact Modeling, and
Electromagnetic Analysis
* Design for Variability, Reliability, Fault Tolerance, Test
* Digital Signal Processing and Image Processing IC Design
* New Devices, MEMS and Microsystems
* Prototyping, Validation, Verification, Modeling and Simulation
* System-On-Chip Design, Digital Architectures
* Embedded Systems Design and Real-Time Systems
* Reconfigurable Systems, Compiler
* Logic and High-Level Synthesis
* Low-Power and Thermal-aware Design


PhD Forum Submission: July 1, 2012
Notification of Acceptance: July 15, 2012


A 1 page abstract of the complete dissertation should be submitted via
the EasyChair conference submission system:

Eligibility: The author must have completed at least one year of a
Ph.D. program. Abstract format:

Presentation: Posters will be presented during a full one-hour Poster
Session. Accepted abstracts will NOT be published by IEEE or ACM.


IFIP WG 10.5
IEEE Circuits and Systems Society
UC Santa Cruz

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Call for Papers: International High-Level Design, Validation and Test Workshop (HLDVT)

HLDVT 2012

IEEE International High-Level Design, Validation and Test Workshop

Huntington Beach, California, November 9-10, 2012

The seventeenth annual workshop HLDVT 2012 aims to bring together a community
of researchers in the areas of design, validation, and test. The workshop addresses
the integration of multiple functions on-chip at higher levels of design abstraction,
and the techniques and methodologies for modeling, analyzing, and validating such systems.
In particular, the workshop has become a unique forum for researchers and practitioners to
discuss the practical issues associated with validation of extremely large designs.

The topics of interest include (but not limited to):

* Simulation-Based Validation
* Formal Verification and Hybrid Methods
* Design Abstraction & Behavioral Modeling
* Error Trace Interpretation and Debugging
* On-Chip and Core-Based Testing
* Test Generation for Defects, Design Errors, and Delay
* Hardware/Software and Mixed-signal System Co-Validation
* Emulation and Prototyping
* Post-silicon Validation and Debug

Paper Submission: The Program Committee invites authors to submit papers not to
exceed 8 pages (IEEE two-column conference format with 10pt minimum font size)
describing original and unpublished work. Panels and special session proposals are
also invited. All submissions must be made electronically in PDF format using
the paper submission webpage: . Please
ensure that all the required contact details are entered during online submission.

Paper Publication and Presenter Registration: The submission of a paper or
panel proposal will be considered as evidence that upon acceptance, the author(s)
will present their paper. For the papers to appear in the program and proceedings,
required is at least one full workshop registration by an author before the submission
of camera-ready version. IEEE reserves the right to exclude a paper from
distribution (e.g., removal from IEEE Xplore) if the paper is not presented at the

Submission deadline: June 24, 2012

Acceptance Notification: August 10, 2012

Final manuscript: September 9, 2012

Questions regarding paper submissions and the program may be addressed
to the program chair: Samar Abdi,
Other questions may be addressed to the general chair: Prab Varma, Additional pertinent information will be made
available at .

Organizing Committee

General Chair
Prab Varma, Apache Design

Program Chair
Samar Abdi, Concordia Univ.

Past Chair
Zeljko Zilic, McGill Univ.

Special Sessions Chair
Franco Fummi, Univ. di Verona

New Topics Chair
Sandeep Shukla, Virginia Tech

Finance Chair
Shireesh Verma, Intel

Tutorials Chair
Chinna Prudvi, Intel

Publications Chair
Marc Boule, Ecole de Tech. Superieure

Web Publicity Co-chairs
Ismet Bayraktaroglu, Sun
Hiren Patel, Univ. of Waterloo

Prabhat Mishra, Univ. Florida

Program Committee

Giovanni Beltrame, Poly Montreal
Jens Brandt, Univ. Kaiserslautern
Ed Cerny, Synopsys
Tim Cheng, UC Santa Barbara
Franco Fummi, Univ. di Verona
Ali Habibi, Qualcomm
Ian Harris, UC Irvine
John Hayes, Univ. of Michigan
Michael Hsiao, Virginia Tech
Alan Hu, Univ. British Columbia
Mohamed Jmaiel, ReDCAD, ENIS
Mohammadreza Mousavi, Eindhoven Univ.
Nicola Nicolici, McMaster Univ.
Priyadarsan Patra, Intel
Alper Sen, Bogazici Univ.
Jean-Pierre Talpin, INRIA
Aiguo Xie, Calypto
Miroslav Velev, Aries Design Automation
Lochi Yu, Univ. Costa Rica
Avi Ziv, IBM

Steering Committee

Bernard Courtois, CMP-TIMA
Masahiro Fujita, Univ. of Tokyo
Prab Varma, Apache Design


HLDVT 2012 is sponsored by the IEEE Computer Society Test Technology Technical
Council and the IEEE CS Design Automation Technical Committee.
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Call for Papers: Work in Progress Session @ International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

Work in Progress Session

The 18th IEEE International Conference on Embedded and
Real-Time Computing Systems and Applications
August 19 to 22, 2012
Seoul, Korea.



Contributions to a special Work-in-Progress (WIP) session of RTCSA'12
are sought. The RTCSA'12 WIP session will be devoted to the presentation
of new and on-going research into real-time systems and applications. We
are especially interested in new and creative ideas and approaches.
Contributors to the WIP session will be asked to give a short presentation
of their work and prepare a poster/demo for the WIP discussion forum that
will be held after the presentations. Accepted submissions will be
included in a special RTCSA'12 WIP proceedings that will be distributed
to all RTCSA'12 conference participants and available electronically
from the Web.

The primary purpose of this session is to provide researchers with an
opportunity to discuss their evolving ideas and gather feedback from the
embedded and real-time community at large. Submissions dealing with all
aspects of embedded and real-time issues are welcome. These include, but
are not limited to:

- System level design and HW/SW co-design
- Embedded system design practices
- Operating systems and scheduling
- Software and compiler issues for heterogeneous multi-core embedded platform
- Embedded system architecture
- Networks-on-chip design
- Power/thermal-aware design issues
- Memory issues for multi-core embedded platform
- Hardware and software techniques for fault tolerance
- Reconfigurable computing architecture and software support

- Real-time operating systems
- Real-time scheduling
- Timing analysis
- Databases
- Programming languages and run-time systems
- Middleware systems
- Design and analysis tools
- Communication networks and protocols
- Case studies and applications
- Media processing and transmissions
- Real-time aspects of Wireless sensor networks
- Energy aware real-time methods

- Real-time issues in ubiquitous computing and cyber-physical systems
- Tools, infrastructures and architectures for ubiquitous computing and cyber-physical systems
- Devices and enabling technologies for ubiquitous computing and cyber-physical systems
- Design and verification methodologies for cyber-physical systems
- Applications of wireless sensor networks
- Ubiquitous computing applications
- Cyber-physical systems applications
- User interfaces and interaction design issues for ubiquitous computing
- Privacy and security issues and implications of ubiquitous computing
- Location-dependent and context-aware computing
- Evaluation methods for ubiquitous computing devices, systems, and applications


Submissions to RTCSA WIP should describe original on-going work.
The material must be unpublished and not under submission elsewhere.
A submission process consists of the below steps:

1) Abstract submission

The abstract submission must include below contents:
- Paper title
- Authors' full names
- Authors' affiliations
- Abstract text (300-400 words)
- Contact information (e-mail addresses)
- Preferred presentation style: poster or demo

The abstract must be sent to in a plain text format.

* Authors can send a PDF file with a main manuscript instead of the abstract-only text,
in advance to the camera ready submission. Please refer the step 3 to format your paper.

2) Acceptance notification

An acceptance notification will be delivered to authors upon the abstract review.

3) Camera ready paper submission

Accepted authors need to prepare a 2 to 4 page camera ready paper for final submission.
The paper must be in the same format as in the final published proceedings
(paper size 8.5" x 11", two-column format, font size 10). The layout
should conform to the IEEE format for conference proceedings (see the
IEEE formatting guidelines
Further instructions will be stated besides the acceptance notification.

If accepted, at least one author will provide a registration, and present the paper at
the conference in person.


Abstract submission deadline: 30th June 2012 (11:59 pm)
Notification: 2nd July 2012
Camera ready copy: 12th July 2012
RTCSA Conference: 19-22nd August 2012

* All dates are in the Korean Standard Time (UTC+9) format.


Chang-Gun Lee, Seoul National University, Korea
Shinpei Kato, Nagoya University, Japan


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