SIGDA E-News 1 September 2012, Vol. 42, No. 9

1 September 2012 :: ACM/SIGDA E-NEWSLETTER :: Vol. 42, No. 9
 Special Interest Group<br />
on Design Automation
1 September 2012, Vol. 42, No. 9
Online archive:
1. SIGDA News
    From: Sudeep Pasricha <>

2. What is Wireless On-Chip Interconnect?
    Contributing authors:
    Ankit More <>, Baris Taskin <>, Drexel University
    From: Srinivas Katkoori <>

3. Paper Submission Deadlines
    From: Debjit Sinha <>

4. Upcoming Conferences and Symposia
    From: Debjit Sinha <>

5. Upcoming Funding Opportunities
    From: Prabhat Mishra <>

6. Call for participation: ACM SIGDA CADathlon 2012
    From: Sudeep Pasricha <>

7. Call for participation: ESWEEK 2012
    From: Ahmed Jerraya <>

8. Call for papers: ISPD 2013
    From: Young Fung Yu <>

9. Call for participation: 2012 CAD Contest
    From: Zhuo Li <>

10. Call for abstracts: MSCAS 2012
    From: Frank Liu <>

11. Call for abstracts: AMS 2012
    From: Frank Liu <>

12. Call for abstracts: VMC 2012
    From: Frank Liu <>

13. Notice of Publication: Special Issue of JECE on ESL Design Methodology
    From: Deming Chen <>
Comments from the Editors

Dear ACM/SIGDA members,

In this issue, we have a very interesting article on Wireless On-Chip
Interconnects. If you are interested in contributing to this column in
the future, please contact Srinivas Katkoori <>.
An article only needs to be about 1 page long with several references.
All articles are included in the ACM digital library and there is no
restriction for the reproduction of the article for printed
publication later.

Sudeep Pasricha, E-Newsletter Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Srinivas Katkoori, E-Newsletter Associate Editor
Prabhat Mishra, E-Newsletter Associate Editor

Back to Contents


"Tokyo court hands Samsung a win over Apple"
A Tokyo court has found Samsung not guilty of infringing Apple's intellectual
property, in contrast to a jury decision and a $1.05 billion damage award in
Apple's favor in a California court last week. Tokyo district court judge
Tamotsu Shoji rejected on Friday (Aug. 31) Apple's claim that Samsung's
products infringe patents related to synchronization of media files. A week
before a nine-person U.S. federal jury had found that many of Samsung's phones
infringe most of two design and three utility patents held by Apple. However,
the U.S. jury found that Samsung's tablets do not infringe Apple's iPad
design patent.

"Top 10 chip vendors hurt by weak 2nd quarter"
Six of the world's top 10 semiconductor suppliers booked chip sales in the
second quarter that were lower than the second quarter of 2011, with four of
the six experiencing double-digit declines, according to market research firm
IHS iSuppli. Global chip sales totaled $75.2 billion in the second quarter,
down 3 percent from the second quarter of 2011, according to IHS. Second
quarter sales improved by less than 3 percent compared with the first quarter,
less than needed to put the industry on a trajectory for growth this year,
IHS said. Last week the firm decreased its outlook for the 2012 chip market,
saying it now expects the market to contract slightly.

"Results from DAC Survey"
Most of the DAC attendees we met were from the U.S., though there was a healthy
number of international visitors to our booth as well. When asked their job
function, most answered “designer” or simply “engineer.” Other job
functions included EDA tool support, management, verification/validation
specialist or system architect. In other words, DAC had a wide range of
attendees, many of whom appeared to be interested in reining in their
verification challenges. On the design side of things, there was no real
surprise –– Verilog was by far the most common HDL language, followed,
in order of preference, by SystemVerilog, VHDL and SystemC. Perhaps a bit
more surprisingly: VHDL beat out Verilog, SystemVerilog and SystemC, in that
order, for testbenches. When asked about simulators, the responses we received
aligned with what those familiar with the EDA industry would expect. The #1
simulator ranked in EDA also came up #1 in our survey. Further, most survey
respondents noted that their companies had either 0-100 simulation seats or
200 plus seats, which parallels the nature of the SoC market –– big and
smaller companies, but not as many in the middle.

"AMD reports progress in cores, SoCs, APIs"
Advanced Micro Devices is making steady progress toward its goal of
transforming itself into a system-on-chip company with broad industry backing
for its chips. AMD expects to announce soon new members of the Heterogeneous
Systems Architecture group it launched earlier this year. HSA could finish
“within months” the first draft of an applications programming interface
for enabling merged graphics, x86 and other cores in SoCs.

"Smartphones projected to be majority of handsets shipped in 2013"
Smartphones are now expected to account for the majority of cellular handset
shipments for the first time in 2013, two years earlier than previously
predicted, according to market research firm IHS iSuppli. According to
an IHS report released Tuesday (Aug. 28), smartphones are now expected to
account for 54 percent of handset shipments in 2013, up from an estimated 46
percent this year and 35 percent in 2011. The firm cites increased demand
from developed regions for high-end smartphones along with an unexpectedly
strong push from emerging economies for lower-cost smartphones.

"Western Digital back on top of hard disk drive heap"
Western Digital Corp. regained the top spot among hard disk drive (HDD)
suppliers in the second quarter, six months after falling behind rival
Seagate Technology Corp. in the wake of flooding in Thailand that forced
several facility closures, market research firm IHS iSuppli said Tuesday
(Aug. 28). Western Digital produced about 71 million HDD units in the second
quarter, generating record revenue for the company of about $4.8 billion,
according to a market brief from IHS. Western Digital's production for the
second quarter includes production from Hitachi GST, which Western Digital
acquired earlier this year, IHS said.

"Xilinx buys embedded Linux tool vendor PetaLogix"
Programmable logic provider Xilinx Inc. said Tuesday (Aug. 28) it acquired
embedded Linux solutions provider PetaLogix. Terms of the deal were not
disclosed. Xilinx (San Jose, Calif.) said the addition of PetaLogix and
itstechnology would strengthen the firm's capabilities and commitment
to customers to provide the best Linux solutions possible for embedded

"Synopsys raises profit target again after strong quarter"
DA and IP vendor Synopsys Inc. Wednesday (Aug. 22) raised its profitability
target for its current fiscal year for a second consecutive quarter after
reporting sale in line with expectations and profitability that exceded
analysts' estimates for the quarter ended last month. "It was a very strong
quarter," said Aart de Geus, Synopsys chairman and co-CEO. "Not only did
we exceed on our earnings per share target but we were able to raise our
earnings-per-share guidance for the year." While semiconductor companies in
recent weeks have largely pointed to softening business amid macroeconomic
uncertainty, de Geus said Synopsys and other EDA vendors are less prone
to volatile cyclicality because they cater to R&D, something that is more
difficult for chip vendors to scale back on during typical cycles related
to inventory buildup and other factors.

"Globalfoundries expected to pass UMC in foundry sales"
Globalfoundries Inc. is expected to surpass United Microelectronics Corp. (UMC)
to become the No. 2 semiconductor foundry supplier in 2012, according to
projected ranking of foundry vendors released this week by market research
firm IC Insights Inc. Globalfoundries (Milpitas, Calif.) is expected to
achieve foundry sales of $4.29 billion in 2012, up 23 percent from 2011,
according to a mid-year update of IC Insights' McClean Report. UMC, long the
No. 2 ranked foundry by sales, is expected to report sales for the year of
about $3.78 billion, roughly flat with 2011, according to the report. Taiwan
Semiconductor Manufacturing Co. Ltd. (TSMC) is expected to remain by far the
dominant player in foundry, with sales projected to increase 15 percent this
year to $16.72 billion, according to the report.

"Mentor sues EVE—again" news/4394310/Mentor-sues-EVE-again
EDA vendor Mentor Graphics Corp. said Friday (Aug. 17) it filed another
patent infringement suit against French emulation tool vendor EVE SA,
the latest in an escalating legal battle between the two companies that
has simmered for years. Mentor (Wilsonville, Ore.) said its latest suit,
filed in U.S. District Court in Oregon, alleges that EVE products violate
Mentor's U.S. patent No. 6,947,882. The patent, entitled "Regionally Time
Multiplexed System" was issued in September 20 2005, Mentor said. The latest
suit seeks to recover damages and to bar the manufacture and sale of the
allegedly infringing products, Mentor said.

"Microelectronics Olympiad backed by Synopsys, IEEE"
It won't be speed over 100-meters but knowledge about microelectronics at
the nanometer-scale that will determine the winners in a competition to take
place in Yerevan, the capital of Armenia, later this year. The idea behind the
forthcoming electronic engineering competition is to turn microelectronics
engineers into medal winners and inspire the next generation to enter the
electronics industry. The Seventh Annual International Microelectronics
Olympiad of Armenia will be held on October 4, 2012 in, Yerevan, Armenia, and
will be held in cooperation with the Institute of Electrical and Electronics
Engineers (IEEE) Test Technology Technical Council (TTTC). Initiated in 2006,
the Olympiad is held under the patronage of the Armenia prime minister and
Synopsys Armenia CJSC is the general organizer and a sponsor.

"ST forms joint venture with Chinese car maker"
Europe's largest chip company STMicroelectronics (Geneva, Switzerland) and
Chinese automobile maker FAW Group Corp. (Changchun, China) have formed a joint
laboratory to conduct research into multiple aspects of automotive electronics
and develop components. State-owned FAW is China's oldest vehicle maker and
produces trucks, buses, special vehicles and sedans. It was established in
1953 and sold more than two million vehicles in 2011. As part of the deal
with ST FAW will adopt ST's microcontrollers (MCUs) and application-specific
standard products (ASSPs) and software while the joint venture will research
power train, chassis, safety, car body, car infotainment, and new-energy
technologies, as well as other automotive applications.

"Intel gives peek inside Xeon Phi at Hot Chips"
Intel provided the first look inside its Xeon Phi aka Knights Corner processor
in a Hot Chips paper here. The chip packs more than 50 quad-threaded
Pentium-class cores with 512-bit vector units and about 25 Mbytes cache
around a 512-bit, three-ring interconnect. Xeon Phi is essentially an x86
symmetrical multiprocessing system on a chip. It runs popular programming
environments used in large server clusters and supercomputers such as OpenMP,
MPI, OpenCL, Pthreads and Intel’s existing tools.

"Chip market now seen shrinking in '12"
A key market watcher is expected to announce Friday (Aug. 24) a downgraded
2012 chip market forecast projecting sales to decline slightly compared to
2011. Based on weak economic conditions and a corresponding reduction in demand
for PCs and other electronics, IHS iSuppli (Englewood, Colo.) now expects
semiconductor sales to contract by 0.1 percent compared to 2011. The projection
is based on preliminary results from the firm's IHS iSuppli Application
Market Forecast Tool (AMFT). Previously, the IHS AMFT had forecast marginal
chip market growth of less than 3 percent. If the projection is accurate,
2012 will mark the first year of decline for the chip market since 2009.

"Automotive IC sales roll, vehicle content up to $350"
If there's a bright spot in the semiconductor industry's lackluster year,
it's the automotive industry, where IC sales are riding the wave of increased
new-car sales and the semiconductor content in vehicles is at record levels,
according to new report. The research firm Databeans reported today (Aug. 23)
that semiconductor content in vehicles has been growing at "double-digit" rates
in recent years and will reach roughly $350 per vehicle this year. "Although
high-end luxury cars have significantly higher semiconductor content than
mid-range or economy vehicles, many optional features are now becoming
standard on mid-range cars," Databeans said, adding the "trickle-down effect
appears to be quickening. "Much of this comes from mega trends like increased
wireless connectivity, energy savings, and safety."

"Intel partners with VMware on cloud security"
Intel Corp. will collaborate with VMware Inc. to deliver a platform for
"trusted cloud" that combines Intel's Trusted Execution Technology (TXT)
and VMware's vSphere 5.1, platform for building cloud infrastructures, Intel
said Monday (Aug. 27). Intel (Santa Clara, Calif.) said its hardware-enhanced
security capabilities integrated directly into the processor combined with
vSphere 5.1 would provide a hardened and high-integrity platform to run
business-critical applications in private and public cloud environments.

Back to Contents

What is Wireless On-Chip Interconnect?
Ankit More and Baris Taskin
Drexel University

Wireless on-chip interconnects are a radio-frequency (RF) alternative
to metal interconnects for global communication on an IC. RF
interconnect channels are based on:

1. On-chip micro-strip transmission lines [1],
2. On-chip antennas [2],
3. On-chip inductors based inductive coupling [3],
4. On-chip capacitors based capacitive coupling [4].

The micro-strip lines are used as guided-wave RF interconnects (RF-I[1])
on a layer for lateral communication whereas the other three are
configured as wireless RF interconnects used for lateral or vertical

The wireless interconnects are not envisioned to antiquate the metal
based interconnects but rather to be implemented in conjunction to
provide hybrid communication structures and networks-on-chip (NoC),
particularly for 2D or 3D multi-processor system-on-chips (MPSoCs).
The design of the wireless RF interconnects for all systems in general
but for multi-core systems in particular requires considerations
across a vast variety of subjects including, electro-magnetic theory,
network theory, wireless communication, VLSI design and design
automation. The multi-faceted design considerations are categorized
according to three primary design paradigms [5]:

P-1) Information Networking Paradigm: The information networking
paradigm considers higher level hybrid architectural design variables:
(a) the architecture of the hybrid NoC using the wireless interconnects,
(b) the number of wireless nodes and the arbitration protocol,
(c) the placement of the wireless nodes in a given network topology
constrained to the maximum possible communication distance,
(d) the protocol to select the wireless short-cut path over the wired

It is proposed in [6], for instance, that the entire network be broken
up into subnets of computational cores with top-level hubs connected
with wireless ports for the high speed links conforming to a
small-world topology. Protocols for a collision free and quality of
service (QoS)-aware hybrid wireless NoCs, in presence of multiple
antennas at the same carrier frequency, are presented in [7].

P-2) Physical Implementation Paradigm: The physical implementation
paradigm considers both the antenna design and the transceiver
design. The antenna and the transceiver design depend on:
(a) the carrier frequency and the required bandwidth,
(b) the maximum communication distance,
(c) the maximum power dissipation,
(d) the output power of the transmitter and sensitivity of the
(e) the electro-magnetic compatibility (EMC) and the electro-magnetic
interference (EMI) of the wireless system with the other on-chip

A silicon implementation of a wireless interconnects system at 15GHz
is presented in [2]. Dynamic reconfiguration of the wireless links
between multiple frequencies is proposed in [8]. Design guidelines
for reducing the impact of on-chip metal structures
(i.e. interconnects and vias) on the performance and characteristics
of the on-chip antennas are provided in [9].

P-3) Wireless Communication Paradigm: The wireless communication
paradigm models the communication channel. It provides the model for
the path loss between the antenna pair and the signal to noise ratio
(SNR) requirement based on the required bit-error-rate (BER) from the
wireless communication channel. The SNR places constraints on:
(a) the maximum wirelessly communicable distance,
(b) the required output power from the transmitter,
(c) the required sensitivity of the receiver.
These constraints in turn determine the power requirements of the
transceiver. The SNR requirement can be eased by utilizing
error-correction coding (ECC).

The wireless interconnect channel is modeled and characterized for the
path loss and delay spread in [10] and the BER and SNR for the
wireless interconnect system are analyzed in [11] and [12],

In summary, the design of the hybrid NoC architectures using wireless
on-chip interconnects can potentially provide high throughput and
energy savings in 2D and 3D MPSoCs. However, their adaptability and
benefits depend on the integration of the multiple facets involved in
the design of such complex systems.


[1] M. F. Chang, V. P. Roychowdhury, L. Zhang, H. Shin and Y. Qian,
"RF/Wireless Interconnect for Inter- and Intra-chip Communications,"
Proceedings of the IEEE, vol. 89, pp. 456-466, April 2001.

[2] B. A. Floyd, C.-M. Hung and K.K. O, "Intra-chip Wireless
Interconnect for Clock Distribution Implemented with Integrated
Antennas, Receivers and Transmitters," IEEE Journal of Solid-State
Circuits, vol. 37, pp. 543-551, May 2002.

[3] N. Miura et al., "A 0.14pJ/b inductive-coupling transceiver with
digitally-controlled precise pulse shaping," IEEE Journal of
Solid-State Circuits, pp. 285-291, January 2008.

[4] A. Fazzi et al., "3D capacitive interconnections with mono- and
bi- directional capabilities," IEEE Journal of Solid-State Circuits,
pp. 275-284, January 2008.

[5] A. More and B. Taskin, "A Unified Design Methodology for a Hybrid
Wireless 2-D NoC," IEEE International Symposium on Circuits and
Systems (ISCAS), 2012.

[6] S. Deb, A. Ganguly, K. Chang, P. Pande, B. Beizer, and D. Heo,
"Enhancing Performance of Network-on-chip Architectures with
Millimeter-wave Wireless Interconnects," IEEE International Conference
on Application-specific Systems Architectures and Processors (ASAP),
2010, pp. 73-80.

[7] D. Zhao and Y. Wang, "SD-MAC: Design and Synthesis of a Hardware-
Efficient Collision-free QoS-aware MAC Protocol for Wireless
Network-on- chip," IEEE Transactions on Computers, vol. 57,
pp. 1230-1245, 2008.

[8] A. More and B. Taskin, "EM and Circuit Co-simulation of a
Reconfigurable Hybrid Wireless NoC on 2D ICs," IEEE International
Conference on Computer Design (ICCD), 2011, pp. 19-24.

[9] A. B. M. H. Rashid et al., "Interference Suppression of Wireless
Interconnection in Si Integrated Antenna," IEEE International
Interconnect Technology Conference (IITC), 2002, pp. 173-175.

[10] M. Sun, Y. P. Zhang, G. X. Zheng, and W. Y. Yin, "Performance of
intra-chip wireless interconnect using on-chip antennas and UWB
radios," IEEE Transactions on Antennas and Propagation, vol. 57,
pp. 2756-2762, September 2009.

[11] Y. P. Zhang, "Bit-error-rate Performance of Intra-chip Wireless
Interconnect Systems," IEEE Communications Letters, vol. 8, pp. 39-41,
January 2004.

[12] D. Bravo et al., "Estimation of the Signal-to-noise Ratio for
On-chip Wireless Clock Signal Distribution," IEEE International
Interconnect Technology Conference (IITC), 2000, pp. 9-11.

Back to Contents

Paper Submission Deadlines

DATE'13 - Design Automation and Test in Europe
Grenoble, France
Deadline: Sep 9, 2012
Mar 18-22, 2013

ISSCC'13 - Int'l Solid-State Circuits Conference
San Francisco, CA
Deadline: Sep 10, 2012
Feb 17-21, 2012

ISQED'13 - Int'l Symposium on Quality Electronic Design
Santa Clara, CA
Deadline: Sep 12, 2012
Mar 11-13, 2013

ISCAS'13 - Int'l Symposium on Circuits and Systems
Beijing, China
Deadline: Sep 28, 2012
May 19-23, 2013

ISPD’13 – Int’l Symposium on Physical Design
(co-located with TAU’13)
Lake Tahoe, CA
Mar 24-27, 2013
Deadline: Oct 1, 2012

ASYNC'13 – Int’l Symposium on Asynchronous Circuits and Systems
Santa Monica, CA
Deadline: Dec 14, 2012 (Abstracts due: Dec 7, 2012)
May 19-22, 2013

MSE'13 - Microelectronics Systems Education
Austin, TX
Deadline: Jan 15, 2013
Jun 2-3, 2013

Back to Contents

Upcoming Conferences and Symposia

PACT'12 - Int'l Conference on Parallel Architectures and Compilation
Minneapolis, MN
Sep 21-25, 2012

BodyNets'12 – Int’l Conference on Body Area Networks
Oslo, Norway
Sep 24-26, 2012

VLSI-SoC’12 – Int’l Conference on Very Large Scale Integration and
System on Chip
Santa Cruz, CA
Oct 7-12, 2012

ESWEEK'12 - Embedded Systems Week (CASES, CODES+ISSS, and EMSOFT)
Tampere, Finland
Oct 7-12, 2012

Wireless Health’12
San Diego, CA
Oct 22-25, 2012

ICCAD’12 – Int’l Conference on Computer-Aided Design
San Jose, CA
Nov 5-8 2012

HLDVT’12 – Int’l High-Level Design, Validation and Test Workshop
Huntington Beach, CA
Nov 9-10, 2012

BIOCAS'12 - Biomedical Circuits and Systems Conference
Hsinchu, Taiwan
Nov 28-30, 2012

MICRO'12 - Int'l Symposium on Microarchitecture
Vancouver, Canada
Dec 1-5, 2012

ICFPT'12 - Int'l Conference on Field-Programmable Technology
Seoul, Korea
Dec 10-12, 2012

ICPADS'12 - Int'l Conference on Parallel and Distributed Systems
Singapore, Singapore
Dec 17-19, 2012

HiPC'12 - Int'l Conference on High Performance Computing
Pune, India
Dec 18-21, 2012

ISED’12 – Int’l Symposium on Electronic System Design
Kolkata, India
Dec 19-22, 2012

VLSI'13 - Int'l Conference on VLSI Design
Pune, India
Jan 5-10, 2013

HiPEAC'13: Int'l Conference on High Performance Embedded Architectures &
Berlin, Germany
Jan 21-23, 2013 hipeac2013

ASP-DAC'13 - Asia and South Pacific Design Automation Conference
Yokohama, Japan
Jan 22-25, 2013

Back to Contents

Upcoming Funding Opportunities


Office of Naval Research (ONR) Summer Faculty Research Program
Deadline: December 05, 2012

National Defense Science and Engineering Graduate (NDSEG) Fellowship Program
Deadline: December 16, 2012

Office of Naval Research (ONR) Sabbatical Leave Program
Deadline: Continuous

Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Deadline: Continuous


Advanced Computing Initiative (ACI)
Deadline: September 12, 2012

Robust Computational Intelligence - AFOSR-BAA-2012-01
Deadline: Continuous oppId=88213&mode=VIEW

Systems and Software - AFOSR-BAA-2012-01
Deadline: Continuous mode=VIEW&oppId=158973

ERDC BAA - Computational Science and Engineering (ITL-1)
Deadline: Continuous

Advanced Distributed Sensor Technologies - BAA 57-09-06
Deadline: Continuous

Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
Deadline: Continuous

High Performance Computing on Massively Parallel Architectures (BAA 64-09-01)
Deadline: Continuous

ASEE-NRL Postdoctoral Fellowship Program
Deadline: N/A

Multidisciplinary University Research Initiative (MURI)
Deadline: September 15, 2012


Early Career Research Program
Pre-application Deadline: September 06, 2012 mode=VIEW&oppId=106293

Director's Postdoctoral Fellows
Deadline: Continuous

Postdoctoral Appointments
Deadline: N/A

Sabbaticals and Faculty Appointments
Deadline: continuous

McDonnell Foundation

Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Deadline: continuous

Alfred P. Sloan Foundation

Sloan Research Fellowships
Deadline: September 15, 2012


Research Experiences for Undergraduates (REU)
Deadline: September 15, 2012 pims_id=5517

National Robotics Initiative (NRI)
Deadline: October 01, 2012 pims_id=503641

Information and Intelligent Systems (IIS): Core Programs
Deadline: Oct 9 (medium) / Nov 30 (large) / Dec 17 (small), 2012 pims_id=13707

Computer and Network Systems (CNS): Core Programs
Deadline: Oct 9 (medium) / Nov 30 (large) / Dec 17 (small), 2012 pims_id=12765

Computing and Communication Foundations (CCF): Core Programs
Deadline: Oct 9 (medium) / Nov 30 (large) / Dec 17 (small), 2012 pims_id=503220

CISE Computing Research Infrastructure (CRI)
Deadline: October 23, 2012 pims_id=12810

Energy, Power and Adaptive Systems (EPAS)
Deadline: November 1, 2012 pims_id=13380

Communications, Circuits, and Sensing-Systems (CCSS)
Deadline: November 1, 2012 pims_id=13381

Research and Evaluation on Education in Science and Engineering (REESE)
Deadline: Continuous pims_id=13667

Back to Contents

Call for participation: ACM SIGDA CADathlon 2012

ACM SIGDA CADathlon 2012
Sunday, November 4

The CADathlon is a challenging, all-day, programming competition
focusing on practical problems at the forefront of Computer-Aided
Design, and Electronic Design Automation in particular. The contest
emphasizes the knowledge of algorithmic techniques for CAD
applications, problem-solving and programming skills, as well as

In its eleventh year as the "Olympic games of EDA," the contest brings
together the best and the brightest of the next generation of CAD
professionals. It gives academia and the industry a unique perspective
on challenging problems and rising stars, and it also helps attract
top graduate students to the EDA field.

The contest is open to two-person teams of graduate students
specializing in CAD and currently full-time enrolled in a
Ph.D. granting institution in any country. Students are selected
based on their academic backgrounds and their relevant EDA programming
experiences. Travel grant s are provided to qualifying students.The
CADathlon competition consists of six problems in the following areas:

(1) Circuit analysis
(2) Physical design
(3) Logic and behavioral synthesis
(4) System design and analysis
(5) Functional verification
(6) Bio-EDA

More specific information about the problems and relevant research
papers will be released on the Internet one week prior to the
competition. The writers and judges that construct and review the
problems are experts in EDA from both academia and industry. At the
contest, students will be given the problem statements and example
test data, but they will not have the judges' test data. Solutions
will be judged on correctness and efficiency. Where appropriate,
partial credit might be given. The team that earns the highest score
is declared the winner. In addition to handsome trophies, the first
place team's prize is a $2,000 cash award. The second place team's
prize is a $1,000 cash award.

Contest winners will be announced at the ICCAD Opening Session on
Monday morning and celebrated at the ACM/SIGDA Dinner and Member
Meeting on Monday evening.

The CADathlon competition is sponsored by ACM/SIGDA and several
Computer and EDA companies. For detailed contest information and
sample problems from last year's competition, please visit the ACM/
SIGDA website at


October 3 Participation request for submission due
October 8 Notification of acceptance


Chair, Jarrod Roy,
Vice Chair, Asst. Prof. Sudeep Pasricha,
Vice Chair, Assoc. Prof. Srinivas Katkoori,
Vice Chair, Sudarshan Banerjee,
Vice Chair, Luis Angel D. Bathen,

Back to Contents

Call for participation: ESWEEK 2012

Tampere, Finland, October 7-12, 2012

Embedded Systems Week is an exciting event which brings together conferences,
tutorials, and workshops centered on various aspects of embedded systems
research and development. Leading conferences in the area will take place
at the same time and location, allowing attendees to benefit from a wide
range of topics covered by these conferences and their associated tutorials
and workshops.

One registration, three conferences

Registered attendees will be allowed to attend sessions in the other
conferences and tutorials for free: CASES 2012, CODES+ISS 2012, EMSOFT
2012. Please note that workshops may require separate registration.


- International Conference on Compilers, Architecture, and Synthesis for
Embedded Systems, chaired by Vincent Mooney and Rodric Rabbah
- International Conference on Hardware - Software Codesign and System
Synthesis, chaired by Franco Fummi and Naehyuck Chang
- International Conference on Embedded Software, chaired by Florence Maraninchi
and John Regehr

Industrial sessions and panels

•Trends in Automotive Embedded Systems
•Internet-of-Energy - Combining Embedded Computing and Communication for
the Smart Grid
•Research issues in smart phones, notepads and related services
•"Low power high performance computing - How could this trend help embedded
systems technology?"


•Monday: Wireless Innovations for Smartphones. Speaker: Dr. Hannu Kauppinen,
Vice President, Head of Nokia Research Center
•Tuesday: Computing without Processors. Speaker: Prof. Satnam Singh,
Technical Infrastructure division, Google, USA
•Wednesday: A Standards-Based, Fully-Open Software Platform for Smart
Embedded Systems. Speaker: Dr. Jong-Deok Choi, Executive Vice President,
Samsung Electronics, Korea


•Analytical Approaches for Performance Evaluation of Networks-on-Chip
Organizer: Axel Jantsch; Speakers: Abbas Eslami Kiasari, Alan Burns, Axel
Jantsch, Marco Bekooij, Zhonghai Lu
•Embedded Reconfigurable Architectures
Organizer: Stephan Wong; Speakers: Stephan Wong, Luigi Carro, Roberto Giorgi,
Stamatis Kavvadias, Stefanos Kaxiras, Georgios Keramidas, Francesco Papariello,
Claudio Scordino
•Coarse-Grained Reconfigurable Architectures - Compilation and Exploration
Organizer: Tom Vander Aa; Speakers: Tom Vander Aa, Panagiotis Theocharis
•Soft Errors: The Hardware-Software Interface
Organizer: Kyoungwoo Lee; Speakers: Kyoungwoo Lee, Reiley Jeyapaul, Aviral
•Runtime Verification of Real-time Embedded Systems
Organizer: Borzoo Bonakdarpour; Speakers: Borzoo Bonakdarpour, Sebastian
•Mixed critical system design and analysis
Organizer: Rolf Ernst;Speakers: Rolf Ernst, Alan Burns, Jimmy Le Rhun,
Lothar Thiele


•CASA 2012: 8th Workshop on Compiler Assisted System-on-chip Assembly ;
Organizer: Aviral Shrivastava
•ESTIMedia 2012: 10th IEEE Symposium on Embedded Systems for Real-Time
Multimedia; Organizers: Jian-Jia Chen , and Maurizio Palesi
•RSP 2012: IEEE International Symposium on Rapid System Prototyping;
Organizers: Fabiano Hessel, Jérôme Hugues and Frédéric Rousseau.
•WSS 2012: Workshop on Software Synthesis; Organizers: Peter Marwedel and
Alberto Sangiovanni-Vincentelli.
•WESE 2012: Workshop on Embedded and Cyber-Physical Systems Education;
Organizers: Peter Marwedel, Jeff Jackson, and Kenneth Ricks.
•EON 2012: Workshop on Optimization of Computing at the Edge of Network;
Organizers: Shahrokh Daijavid, Sumedh Sathaye and Seraphin Calo
•WESS 2012: Workshop on Embedded Systems Security; Organizers: Dimitrios
•MeCoES 2012: Workshop Metamodeling and Code Generation for Embedded Systems;
Organizers: Wolfgang Mueller and Wolfgang Ecker
•MeAOW 2012: Memory Architecture and Organization Workshop; Organizers:
Jason Xue and Nikil Dutt

Co-located Events

SoC 2012: International Symposium on System-on-Chip 2012, October 11-12, 2012.

Registration is now open at

Contacts: ESWeek General Chairs: - Ahmed Jerraya, CEA, France; Luca Carloni,
Columbia University, USA
ESWeek Local Arrangement Chair: - Jari Nurmi, Tampere University of Technology,

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Call for papers: ISPD 2013

ACM International Symposium on Physical Design 2013
With a tribute to Professor Yoji Kajitani

Submission deadline: October 1, 2012
Acceptance notification: November 14, 2012
Camera-ready paper due: January 16, 2013
Symposium date: March 24 - 27, 2013

Location: To be announced shortly.
(Co-located with TAU,
Sponsored by ACM SIGDA with Technical Co-sponsorship from IEEE CAS

The International Symposium on Physical Design provides a premier forum
to exchange ideas and promote research on critical areas related to the
physical design of VLSI systems. All aspects of physical design,
including its interactions with architecture, behavioral- and logic-level
synthesis, and back-end performance analysis and verification are within
the scope of the symposium. Target domains include semi-custom and
full-custom IC's, regular fabrics, FPGA's, and
systems-on-chip/systems-in-package. Following its twenty-one predecessors,
the 2013 symposium will highlight key new directions and leading-edge
theoretical and experimental contributions to the field. The ACM Press
will publish accepted papers in the Symposium proceedings. Topics of
interest include but are not limited to:

- Floorplanning and interconnect planning
- Interactions with behavior-level synthesis flows
- Partitioning, placement and routing
- Interactions with logic-level (re-)synthesis flows
- Physical design for manufacturability and yield
- Analysis and management of power dissipation
- Synthesis optimizations within physical design
- Management of design data and constraints
- Estimation and modeling
- New physical design methodologies
- Timing and crosstalk issues in physical design
- New paradigms in physical design
- Special structures for clocking and power networks
- Circuit performance measurements in a PD context
- Physical design for emerging process technologies
- Multithreaded/distributed algorithms in physical design
- Makeover of traditional PD problem formulation for the new technology nodes
and new applications
- Critiques and in-depth analysis of previously published PD algorithms with
new experimental results for better comparison

Continuing the tradition of spirited competition for the previous eight ISPD
contests, a contest will be held in ISPD 2013. Details will be announced on
our website later.


All papers must be submitted electronically. Details will be posted on the
website . Potential authors will be required to submit
full-length, original, unpublished papers (a maximum of 8 pages in ACM
conference format) along with an abstract of at most 200 words and contact
author information (name, street/mailing address, telephone/fax, e-mail).
Previously published or papers concurrently submitted for publication to other
conferences/journals will not be considered. If one or more related papers
have been previously published elsewhere or have been concurrently submitted
elsewhere for publication, the authors should clearly state the differences
between these papers and the current submission. All submitted papers will be
under blind reviews, and thus they must not include name(s) or affiliation(s)
of the author(s) anywhere in the manuscripts. Failure to comply with these
requirements will result in automatic rejection.

ISPD will recognize excellent contributions through a Best Paper Award.


General Chair: Cheng-Kok Koh (Purdue Univ.) []
Steering Committee Chair: Jiang Hu (Texas A&M Univ.) []
Technical Program Chair: Cliff Sze (IBM) []
Publications Chair: Azadeh Davoodi (Univ. Wisconsin) []
Publicity Chair/Webmaster: Evangeline F. Y. Young (Chinese Univ. of Hong Kong)
Contest Chair: Mustafa Ozdal (Intel) []

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Call for participation: 2012 CAD Contest

Call for participation

The annual CAD Contest in Taiwan, sponsored by the Ministry of Education
(MOE), has been held for 12 consecutive years and has successfully boosted
the EDA research momentum in Taiwan. In 2012, we continue this great
tradition and internationalize it under the joint sponsorship of IEEE CEDA
and Taiwan MOE. The new contest, 2012 CAD Contest at ICCAD, is open
worldwide to have more significant contributions to our global EDA
community. You are invited to participate!


In the first year (2012), we design three contest problems covering three
distinct areas:

1. Finding the minimal logic difference for functional ECO contributed by
Taiwan Cadence Design Systems, Inc.
2. Design hierarchy aware routability-driven placement contributed by IBM
3. Fuzzy pattern matching for physical verification contributed by Mentor
Graphics Corp.


1. The contestants should be university students.
2. Contestants must register by August 16, 2012.
3. Changes of team members, advisors or topics should be made by the
deadline of registration.

Evaluation and ranking

1. Each topic is ranked separately.
2. The quality metrics are determined by the problem specifications,
including correctness, runtime and memory usage.
3. Each submitted program will be evaluated by the announced benchmarks and
hidden benchmarks.
4. The officially supported programming language will be C/C++. For other
languages, please check with the contest organizers first. MATLAB is
prohibited for use in the contest.
5. The library that can be used in the contest is the standard C/C++

6. System specification:

Linux version: TBD
Gcc version: TBD
GNU libc version: TBD


1. 1st Place
One team for each topic
- Certificate of 1st Place presented by ICCAD
- NTD50,000/team (approx. US$1650)
2. 2nd Place / 3rd Place
Two teams for each topic
- Certificate of 2nd Place presented by ICCAD
- NTD30,000/team (approx. US$1000)

(a) The reward amount in US dollars fluctuates slightly according to currency
(b)According to the tax law in Taiwan, 10% reward will be charged by tax
for the Taiwanese
taxpayers, while 20% will be charged by tax for foreign taxpayers.
(c)We reserve the right to change the number of prize winners.

Tentative Contest Schedule

1. Registration deadline August 16, 2012
2. Alpha submission 5pm CST (UTC+8), August 23, 2012
3. Submission deadline 5pm CST (UTC+8), September 24, 2012
4. Final announcement November 2012 (at ICCAD)

Other Information

1. For any other inquiries, please send emails to:
2. Please add "ICCAD2012_Contest" to the subject line for any emails regarding
the contest.
3. Any update will be announced on contest website: ICCAD2012/.
4. There may be a special session organized for the contest at ICCAD 2012
(we will be notified by the end of May). This session includes three
presentations from the contest organizers for the three contest problems and
the award ceremony.


1. Contest chair:
Yih-Lang Li (National Chiao Tung University, Taiwan)

2. Co-chairs:
Iris Hui-Ru Jiang (National Chiao Tung University, Taiwan)
Zhuo Li (IBM, Corp.)

3. Topic chairs:
Jane Wang (Taiwan Cadence Design Systems, Inc.)
Natarajan Viswanathan (IBM Corp.)
Andres Torres (Mentor Graphics Corp.)


1. IEEE CEDA (Technical sponsorship)
2. Taiwan Ministry of Education (Financial sponsorship)

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Call for abstracts: MSCAS 2012

2012 IEEE/ACM Workshop on CAD for
Multi-Synchronous and Asynchronous Circuits and Systems
Nov. 8th, 2012 Hilton San Jose, CA USA
Co-located with ICCAD


Many current integrated circuit designs are partitioned into multiple
timing domains, allowing each domain to be independently optimized for
power and performance. This simplifies timing closure and enables the
integration of IP blocks with different timing requirements. One
system approach is to use traditional handshaking circuits naturally
employ locally generated timing signals that can yield high
performance or provide fine-grained activity gating for low power.
GALS methods where the asynchrony appears at the level of system
integration are another approach.

Multi-synchronous and asynchronous architectures present design
challenges and require supportive CAD that arise when departing from
the timing methodology and determinism of single frequency synchronous
designs. While the departure is already well underway, more
systematic CAD support for these designs promises lower power, higher
robustness, and better performance. Such a new generation of CAD also
enables a much wider base of designers to exploit these advantages.

This workshop provides a forum to discuss current challenges of
asynchronous design, how to address the CAD problem, and how to gain
penetration of this disruptive technology in industry. This is
intended for both technical and industry experts in the asynchronous,
GALS, elastic-pipelining, and latency insensitive design communities.


- Current state of the art in asynchronous design
- Timing closure, optimization and validation
- Physical design of asynchronous circuits
- Challenges for multi-synchronous/asynchronous design
- Process variation and its role in multi-synchronous design
- Synthesis and system architecture
- Addressing the test challenge
- The role of asynchronous design in multi-clocked designs and DVFS
- Perspectives for/from commercialization
- Solutions to key challenges to asynchronous commercialization


Two page maximum in US Letter or A4 format. One page is strongly
recommended. Once accepted, the authors are required to give a 20
minute presentation as well as provide a poster for discussion and
interaction. There will also be time provided for round table
discussions on the topics.


Submission Deadline: Sep. 24th, 2012
Notification of Acceptance: Oct. 1st, 2012
Workshop Date: Nov. 8th 2012


Please send the abstract in PDF format to with
subject "MSCAS Submission"


Co-Chairs: Ken Stevens, University of Utah
Mark Greenstreet, University of British Columbia

John Bainbridge, Sonics Gary Delp, Mayo Clinic
Jo Ebergen, Oracle Steve Furber, University of Manchester
Mike Kishinevsky, Intel Rajit Manohar, Cornell
Marc Renaudin, Tiempo IC

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Call for abstracts: AMS 2012


International Workshop on Design Automation for Analog and Mixed-Signal
Thursday, November 8, 2012, Co-located with ICCAD 2012
Web Site:
Submission Deadline: September 20, 2012

With the aggressive scaling of advanced IC technologies, today's analog
and mixed-signal (AMS) circuits have become extremely complex. As circuit
designers have adopted a number of non-traditional methodologies (e.g.,
adaptive self-healing, etc) to address the design challenges associated
with technology scaling (e.g., reduced voltage headroom, increased process
variation, etc), the corresponding digital-analog interactions have become
increasingly difficult to verify. These recent trends of AMS circuits have
brought up enormous new challenges and opportunities for AMS CAD. The purpose
of this workshop is to report recent advances on AMS CAD and, more importantly,
motivate new research topics and directions in this area.

Topics of interest include (but not limited to):
* Behavioral and performance modeling at circuit & system levels
* Analog and mixed-signal simulation and verification
* AMS self-healing and post-silicon tuning
* AMS circuit optimization and design space exploration
* PVT variations and reliability for AMS circuits
* AMS testing and diagnosis

Posters that address any of the aforementioned topics are invited. Posters
addressing AMS design issues outside of these areas will also be of great
interest to the workshop. They will be considered equally relevant in review
process. The workshop will NOT publish official proceedings including all

Poster Submission Instructions

To present a poster at the workshop, please submit an abstract to Dr. Jun
Tao ( ) via email. Your submission must include the
following information: (1) poster title, (2) author names and affiliations,
and (3) abstract (up to one page). To be considered in the review process,
your abstract must be submitted by September 20, 2012. Notification of
acceptance will be sent to you on October 1, 2012.

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Call for abstracts: VMC 2012

Call-For-Abstract: 2012 IEEE/ACM Workshop on Variability Modeling and



Variability is emerging as a fundamental challenge to IC design in scaled
CMOS technology; and it has profound impact on nearly all aspects of circuit
performance. While some of the negative effects of variability can be handled
with improvements in the manufacturing process, comprehensive methods are
necessary to assess and manage the negative effects of variability, which
in turn requires accurate and tractable variability models. The goal of the
VMC workshop is to provide a forum for theoreticians and practitioners to
freely exchange opinions on current practices as well as future research
needs in variability modeling and characterization.

The workshop organizers strongly encourage the submission of early results
in the related topics. The submissions will be evaluated by a Technical
Program Committee and the author(s) of the accepted submissions are expected
to present the results in the format of posters at the workshop.

1. Fundamental physics of device variability
2. Compact variability modeling development and application
3. Statistical extraction of variability
4. Variability test structure design and calibration
5. Design interface and solutions for variability
6. Variability issues in emerging semiconductor technology
7. Temporal variability issues
8. Other relevant topics

Technical Program Committee
Co-chairs: Hidetoshi Onodera, Kyoto University; Yu Cao, Arizona State
Asen Asenov, University of Glasgow
Chris Kim, University of Minnesota
Colin McAndrew, Freescale Semiconductor
Vijay Reddy, Texas Instruments
Takashi Sato, Kyoto University

Two page maximum in US Letter or A4 format. One page is strongly encouraged.
Once, the
authors are required to give a short oral introduction as well as poster

Submission Deadline: September 14th, 2012
Notification of Acceptance: September 28th, 2012
Workshop Date: November 8th, 2012

Please send the abstract in PDF format to, with
subject "VMC2012 submission"

Professor Yu Cao, ECE Department, Arizona State University,

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Notice of Publication: Special Issue of JECE on ESL Design Methodology

A special issue of Journal of Electrical and Computer Engineering on ESL Design
Methodology has just been published. It is open access, and all the
articles can
be accessed at:

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Notice to Authors
Notice to Authors

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