SIGDA E-News 1 February 2010, Vol. 41, No. 2

1 February 2010 :: ACM/SIGDA E-NEWSLETTER :: Vol. 41, No. 2

 Special Interest Group on Design Automation

1 February 2010, Vol. 41, No. 2
Online archive:

  1. SIGDA News
        Contributing author: Soheil Ghiasi <>
        Contributing author: Matthew Guthaus <>
        Contributing author: Umit Y Ogras <>
        Contributing author: Marc Riedel <>
        Contributing author: Lin Yuan <>
  2. What is
        Contributing author: Reinaldo Bergamaschi <>
        From: Mehmet Yildiz <>
  3. Paper Submission Deadlines
        From: Debjit Sinha <>
  4. Upcoming Conferences and Symposia
        From: Debjit Sinha <>
  5. Upcoming Funding Opportunities
        From: Sudeep Pasricha <>
  6. Call for Demonstrations: ACM/SIGDA University Booth at DAC
        From: Naehyuck Chang <>
  7. Call for Papers: IEEE/ACM International Symposium on Low Power Electronics and Design
        From: Naehyuck Chang <>
  8. Call for Papers: Workshop on Green Multimedia Communication
        From: Yung-Hsiang Lu <>
  9. Call for Papers: IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2011)
        From: Janet Wang <>
  10. Call for Papers: ACM Journal on Emerging Technologies in Computing Systems Special Issue on Asynchrony in System Design
        From: Montek Singh <>
  11. Design Contest: 11th International Low Power Design Contest
        From: Naehyuck Chang <>

Comments from the Editors

Dear ACM/SIGDA members,

Happy New Year!

In this issue, we have including an article on "What is"
from a former CAD person you may all know: Dr. Reinaldo
Bergamaschi. Renaldo describes his new web portal that provides a
tool for academic information and technical collaboration. If you
would like to contribute to the "What is..." column in the
E-Newsletter, please feel free to contact us.

The SIGDA would like to thank Soheil Ghiasi who is retiring as an
E-Newsletter Associate Editor.

Matthew Guthaus, E-Newsletter Editor;
Marc Riedel, E-Newsletter Associate Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Umit Y Ogras, E-Newsletter Associate Editor;
Sudeep Pasricha, E-Newsletter Associate Editor;
Mehmet Yildiz, E-Newsletter Associate Editor;

Back to Contents


"What's inside the iPad 2?"
The iPad 2, Apple's next-generation tablet PC, will use ARM's
''Cortex-A9 dual core processor running at 1.2-GHz'' and Imagination’s
SGX543 dual core graphics, according to the AppleInsider Web site,
which cited Concord Securities as its source. Here's the
specifications for the current iPad.

"EDA execs prognosticate on
Whether seen as continued growth or as a soft landing, the group of
EDA leaders saw 2011 neither as a continuation of the explosive return
of 2010 nor as a looming calamity, but as something in between.

"Cadence rolls 28-nm digital design flow"
EDA vendor Cadence Design Systems Inc. Monday (Jan. 31) rolled out an
end-to-end digital design flow for 28-nm based on the company's
Encounter platform. According to Cadence (San Jose, Calif.), the new
Encounter-based flow provides a faster, more deterministic path to
achieve giga-gate/gigahertz silicon through technology integration and
significant core architecture and algorithm improvements in a unified
design, implementation and verification flow.

"IDT says new chips cut touchscreen's cost"
Touchscreens for mobile handsets, personal navigation devices,
handheld gaming platforms and other pocket-sized electronic devices
can be built more inexpensively by adopting a the world's first
single-layer multi-touch capacitive controller, according to
Integrated Device Technology Inc. (IDT).

"Intel finds design error in chip"
Intel has found a design error in a support chip for the recently
announced Sandy Bridge processor. The company says it has implemented
a solution but that the error could cost the company $700 million. The
design error is in the Intel 6 Series support chip, code-named Cougar
Point, that has been shipping since Jan. 9, Intel said.

"Xilinx buys high-level synthesis EDA vendor"
SAN FRANCISCO—Programmable logic vendor Xilinx Inc. Monday (Jan. 31)
said it acquired high-level synthesis vendor AutoESL Design
Technologies Inc. Financial terms of the deal were not disclosed.

"Android Overtakes Symbian as World's No. 1 Smartphone Platform"
Android moved nearly 33 million units last quarter. It's been a long
time coming and should come as no surprise to anyone who has been
tracking Android's meteoric rise -- both in the U.S. and worldwide --
that Google's mobile OS has finally outpaced Nokia's stalwart Symbian
platform as the leading smartphone OS worldwide.

"HP, Apple, Samsung largest chip consumers in 2010"
Semiconductor device vendors must pay attention not just to the design
and purchasing TAM by company, but also to that by region, Garter
says. The top 10 OEMs accounted for $104.3 billion of semiconductors
on a design total available market (TAM) basis, or 34.7% of vendors'
worldwide chip revenue, in 2010, according to Gartner Inc.

"Intel earmarks $100M for US universities, changes academic research model"
Intel changes its university researcher model, planning to invest $100
million directly into US university research and to create Intel
Science and Technology Centers, opposed to running open collaboration
centers near research universities.

"Thermal nanotape aims to cool hot spots"
Researchers develop a nanostructured thermal tape, or nanotape, that
conducts heat like a metal while allowing the neighboring materials to
expand and contract with temperature changes.

"Imec launches research program on high-bandwidth optical I/O"
Imec has announced a new industrial affiliation program on
high-bandwidth optical input/output (I/O) with the primary objective
of exploring the use of optical solutions for realizing high-bandwidth
I/O between CMOS chips.

"Verifying complex clock and reset regimes in modern chips: the challenge and scalable solution"
In an environment where chip-design risks have ballooned to worrying
levels, a verification methodology based on just linting and
simulation does not cut it. Identifying specific sources of
verification complexities and deploying automatic customized
technologies to tackle them in a surgical manner has an enormous

"Expect More Growth in FPGAs As Ecosystem Evolves and Design Methodologies Improve"
By all accounts, 2010 was a record year in terms of year-over-year
growth for the semiconductor industry. This should come as no
surprise, although maybe with a sigh of relief, after a disastrous
2009. And most industry forecasters are calling for more growth in
2011, at significantly slower rates, across almost every semiconductor
application and market sector. Rain or shine, one of the true bright
spots in the forecasts continues to be programmable logic.

"For Anything To Have Wide Adoption, Open Standards Are Must"
Electronic design automation (EDA) plays the most important role in
design and development of any product. Pravin Madhani, general
manager, place and route division of Mentor Graphics, also the founder
of Sierra Design Automation and Everest Design Automation, spoke to
Shweta Dhadiwal of EFY Bureau on what leads to new tool development in
the EDA industry. During the talk at EDA Tech Forum, he also expressed
his views on Open standards and Open Source.

"Unnatural Genes Used to Replace Missing DNA Keep Cells Alive"
Synthetic biology garnered national headlines in May 2010 when a team
led by J. Craig Venter announced it had created the world’s first
“synthetic cell." The group used computers to copy an entire bacterial
genome that, when inserted into a cell whose own genome had been
removed, "booted up" the cell, which then passed the synthesized
genome to its offspring. This accomplishment was no small feat but the
new genome, although man-made, was almost entirely a replication of
one that already existed in nature. Now, a new study published January
4 in PLoS One has shown that DNA sequences designed in the laboratory
and distinct from any found in nature can, when inserted into cells
missing genes necessary for survival, "rescue" some of those cells.

Back to Contents

What is

Reinaldo A. Bergamaschi, Rodrigo Carvalho Rezende, Henrique Przibisczki de
Oliveira, and Paulo Mendes (all at

Odysci ( is a web portal for academic search and technical
collaboration in the computer science, electrical engineering and related areas.
Academic search is a specialized type of search that returns published scholarly
works, ranked according to various criteria.

Before the actual search and rank can be done, there are dozens of tasks that
need to be accomplished, many of which involve significant algorithmic and
computing challenges in the areas of machine learning, similarity and
clustering, graph analysis, information retrieval and databases. This article
briefly introduces the reader to these tasks and informally navigates through
the steps of developing a service like

Main steps for an academic search site (by no means exhaustive): (1) Gather
metadata for articles; (2) Organize data in databases; (3) Handle data
de-duplication; (4) Link analysis and ranking metrics; (5) Information
retrieval, indexing and search; (6) Ranking of articles; (7) Client-server
architecture; and (8) End user interface.

Gather metadata for articles

The first major step in developing an academic search site is the gathering of
metadata for published articles. Metadata includes, for example, title,
publication venue (journal, conference, book), authors, affiliation, abstract,
keywords and references. If the full text is available, it can also be used as
indexable content. The metadata can, in some cases, be obtained directly from
the publishers, from other public repositories, or using crawlers on the
web. Due to the large number of documents being handled, efficient mechanisms
for parallel processing and distributed storage are needed[1].

If an article is obtained as pdf, it must be converted to structured metadata
before it can be imported. This conversion implies converting it to text and
then extracting the relevant metadata from the text, i.e., parse the text and
recognize the names of authors, their affiliations, abstract, body and
individual references. This is generally known as the problem of text
segmentation and labeling[2][3].

Organize data in databases

There are many ways of organizing and storing data in databases. The metadata
components, e.g., title, publication venue, authors, etc., can be organized as a
complex graph structure where a venue points to all its articles, an article
points to its authors and references, authors point to their affiliations and so
on. This whole graph can be referred to as "Digital Library (DL) Object Graph".
Relational databases (e.g., MYSQL) are typically used for storing such
structures. However, as the amount of data grows significantly, other approaches
that lend themselves better to parallel processing and distributed storage have
gained attention[4].

Handle data de-duplication

Very often, the same metadata is received in different forms. Due to different
sources and different extraction processes, the same article may be represented
by two or more metadata files with non-matching fields because of misspelled or
abbreviated names, or wrong extraction from pdfs. In order to avoid duplication
in the database, the software must be able to detect whether or not two records
represent the same article. This problem is generally known as Named Entity

Link analysis and ranking metrics

The most successful web ranking algorithms are based on analysis of the web
graph. The two best known methods that extract the ranking of a web page by
exploring the web graph are PageRank[6] and HITS[7]. Both approaches rely on
the simple premise that a web page is relevant if pointed by other relevant web
pages. The HITS method offered the variation of distinguishing between inlinks
(Authority nodes) and outlinks (Hub nodes) as part of the ranking. Both methods
can be formalized as an eigenvector problem, and solved iteratively (which is
the most efficient way when considering billions of nodes).

These methods can be applied to the ranking of scientific publications, using
the DL Object Graph formed by articles, citations, authors, conferences,
journals, etc. Well known metrics such as H-Index and Impact-Factor can also be
computed for authors and publications respectively.

Information retrieval, indexing and search

Search engines often rely on a specialized data structure called "Inverted
Index" for efficient text-based document search and retrieval. An inverted
index[8] is similar to a hash table where the key is represented by a word and
the value is a list of all documents (i.e., their ids) which contain that word,
known as "Posting list". Given two words in a query, the intersection of the two
lists of document ids, return the ids of the documents containing both words,
whereas the union of both lists return the ids of all documents that contain at
least one of the words. The terms to be indexed may undergo a series of
transformations and expansion in order to cover a multitude of different user
search behaviors. Examples of these transformations are tokenization or grouping
of words, expansion of synonyms, acronyms and abbreviations, stop-word removal
and stemming[9].

An important part of search is the interpretation of the user query. A search on
"Bryant, bdd, DAC" could reasonably be expected to return Bryant's papers on
bdds published at DAC. However, this implies a specific interpretation of the
query that assumes "Bryant" as an author, "bdd" as a topic, and "DAC" as a
conference. In order for this to work, queries must be processed to meet
expected user intent. Techniques for query expansion and rewriting[10] are
interesting research challenges.

Ranking of articles

When a user searches for articles using keywords, the system returns a ranked
list of papers relevant to the keywords used. The ranking of these articles
depends on two major criteria: (1) how well the contents of the article match
the keywords used - called query-dependent metrics, and (2) the ranking of the
articles based on link analysis metrics extracted from the DL Object Graph -
called query-independent metrics. The final ranking of an article will be a
composition of its query-dependent and its query-independent metrics. How
exactly these metrics are combined is usually proprietary information.

Client-Server architecture

A search service may involve several layers of successive requests which can be
handled by one or more servers. The communication between these different
servers can be done using different protocols and services which vary in
complexity, capability and computational load. Examples of these services are
SOAP, WSDL, RESTful. The RESTful service is implemented using HTTP and REST
(Representational State Transfer)[11], and is simple, yet scalable and uses
common Internet media types like XML and JSON, supported by standard HTTP
methods. For these reasons it is a good alternative for the communication
between servers in a search engine.

End user interface

The main principle behind the end-user interface for the Odysci site was easy
accessibility to search results and related information. The goal is to allow
the user to reach any paper, conference, journal, author with the minimum number
of cliques. Part of that is, of course, to be able to rank the results well. But
on top of this, comes the ability to navigate easily through the results. For
example, from the listing of papers (resulting from a search) one can access six
set of data with a single click of the mouse, namely: (a) details about a paper,
(b) references of a papers, (c) list of papers which cite a given paper, (d) the
papers of any listed author, (e) the papers published in a journal or conference
in a given listed year, and (f) all the papers published in a journal or
conference for all the years of publication.


Odysci's main research focuses on developing novel algorithms for data
de-duplication and ranking algorithms, since we consider the quality of our data
and ranking important aspects for the user. The web site also offers facilities to
foster interaction among researchers, such as the ability to comment on
papers. Users can also follow papers and get alerts about them (such as when a
paper you follow is cited by a new paper). An Online Editorial Board of renowned
experts will provided regular comments about their favorite papers. Odysci
currently covers computer science, electrical engineering and related areas. We
currently list almost 2 million documents (or about 65 million nodes in the DL
Object Graph), including data from ACM, IEEE Computer Society, several other
public databases and data gathered using crawlers. New conferences and journals
are added on a weekly basis.

We would like to invite the computing community to try out for
search of research papers.
twitter @odysci


[1] "The Hadoop Distributed File System", Konstantin Shvachko et al., 2010
IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST), 2010.
[2] "Conditional Random Fields: Probabilistic Models for Segmenting and Labeling
Sequence Data", John D. Lafferty et al., 18th International Conference on
Machine Learning (ICML 2001), 2001.
[3] "Maximum Entropy Markov Models for Information Extraction and Segmentation",
Andrew McCallum et al., 17th International Conference on Machine Learning (ICML
2000), 2000.
[4] "Cassandra: A Structured Storage System on a P2P Network", Avinash Lakshman
et al., presentation at SIGMOD 2008
[5] "Duplicate Record Detection: A Survey", Ahmed .K. Elmagarmid et al., IEEE
Transactions on Knowledge and Data Engineering, vol. 19, no. 1, 2007.
[6] "The PageRank Citation Ranking: Bringing Order to the Web", Larry Page et
al., Technical Report 1999-0120, CS Dept., Stanford University, 1999.
[7] "Authoritative Sources in a Hyperlinked Environment", Jon M. Kleinberg,
Journal of the ACM, Vol.46, No.5, September 1999.
[8] "Inverted files for text search engines", Justin Zobel and Alistair Moffat,
ACM Computing Surveys, vol.38, no.2, July 2006.
[9] "Text Operations", Chapter 7, "Modern Information Retrieval", Ricardo
Baeza-Yates and Berthier Ribeiro-Neto, 1999, Addison-Wesley.
[10] "Concept-based interactive query expansion", Bruno M. Fonseca et al., 2005
ACM International Conference on Information and Knowledge Management (CIKM), 2005.
[11] "Principled design of the modern Web architecture", Roy T. Fielding and
Richard N. Taylor, ACM Transactions on Internet Technology, vol.2, no.2, May 2002.

Back to Contents

Paper Submission Deadlines

SASP’11 – Symposium on Application Specific Processors
(co-located with DAC’11)
San Diego, CA
Jun 5-6, 2011
Deadline: Feb 21, 2011

ISLPED’11 – Int’l Symposium on Low-Power Electronics and Design
Fukuoka, Japan
Aug 1-3, 2011
Deadline: Mar 7, 2011

SLIP’11 - System Level Interconnect Prediction
San Diego, CA
June 5, 2011
Deadline: Mar 11, 2011 (Abstract submission deadline: Mar 4, 2011)

ACM JETC - Journal on Emerging Technologies in Computing Systems
Special Issue on Asynchrony in System Design
Deadline: Mar 15, 2011

PACT'11 - Int'l Conference on Parallel Architectures and Compilation
Galveston Island, TX
Oct 8-12, 2011
Deadline: Mar 25, 2011 (Abstract submission deadline: Mar 18, 2011)

ASQED'11 - Asia Symposium on Quality Electronic Design
Kuala Lumpur, Malaysia
Jul 19-20, 2011
Deadline: Apr 4, 2011

VLSI-SoC’11 – Int’l Conference on Very Large Scale Integration and System on Chip
Hong Kong, China
Oct 3-5, 2011
Deadline: Apr 4, 2011

24th ACM SIGDA University Booth
(co-located with DAC’11)
San Diego, CA
Jun 5 - 10, 2011
Deadline: May 2, 2011 (tentative)

Back to Contents

Upcoming Conferences and Symposia

ISSCC'11 - Int'l Solid-State Circuits Conference
San Francisco, CA
Feb 20-24, 2011

ISQED'11 - Int'l Symposium on Quality Electronic Design
Santa Clara, CA
Mar 14-16, 2011

DATE'11 - Design Automation and Test in Europe
Grenoble, France
Mar 14-18, 2011

ISPD’11 – Int’l Symposium on Physical Design
Santa Barbara, CA
Mar 27-30, 2011

TAU’11 - International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
(co-located with ISPD’11)
Santa Barbara, CA
Mar 31 – Apr 1, 2011

SPL'11 - Southern Conference on Programmable Logic
Cordoba, Argentina
Apr 13-15, 2011

ASYNC'11 - Intl. Symposium on Asynchronous Circuits and Systems
Ithaca, NY
Apr 27-29, 2011

ISCAS'11 - Int'l Symposium on Circuits and Systems
Rio De Janerio, Brazil
May 15-18, 2011

ISCA’11 – Int’l Symposium Computer Architecture
San Jose, CA
Jun 4-8, 2011

SLIP’11 - System Level Interconnect Prediction
San Diego, CA
June 5, 2011

DAC’11 – Design Automation Conference
San Diego, CA
Jun 5-10, 2011

SASP’11 – Symposium on Application Specific Processors
(co-located with DAC’11)
San Diego, CA
Jun 5-6, 2011

AHS’11 - NASA/ESA Conference on Adaptive Hardware and Systems
(co-located with DAC’11)
Jun 6-9, 2011
San Diego, CA

MSE'11 - Microelectronics Systems Education
San Diego, CA (co-located with DAC’11)
Jun 5 - 6, 2011

24th ACM SIGDA University Booth
(co-located with DAC’11)
San Diego, CA
Jun 5 - 10, 2011

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Upcoming Funding Opportunities


Office of Naval Research (ONR) Sabbatical Leave Program
Deadline: N/A

Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Deadline: Continuous


Microsystems Technology Office-Wide Broad Agency
Announcement - DARPA-BAA-10-35
Deadline: Continuous


Cognitive Neuroscience
Deadline: March 25, 2011

Biomimetic Signal Processing and Control - BAA-RWK-10-0001
Deadline: Continuous through April 30, 2011

Hardware-in-the-Loop Simulation Technologies - BAA-RWK-10-0001
Deadline: Continuous through April 30, 2011

ARL/ARO Core Broad Agency Announcement for Basic and Applied
Scientific Research for Fiscal Years 2007 through 2011
Deadline: Continuous through September 30, 2011\

Robust Computational Intelligence - AFOSR-BAA-2010-01
Deadline: Continuous

Systems and Software - AFOSR-BAA-2010-01
Deadline: Continuous

ERDC BAA - Computational Science and Engineering (ITL-1)
Deadline: Continuous

Advanced Distributed Sensor Technologies - BAA 57-09-06
Deadline: Continuous

Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
Deadline: Continuous

High Performance Computing on Massively Parallel Architectures
(BAA 64-09-01)
Deadline: Continuous

ASEE-NRL Postdoctoral Fellowship Program
Deadline: N/A


Postdoctoral Appointments
Deadline: N/A

McDonnell Foundation

Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Deadline: continuous


Engineering Design and Innovation (EDI)
Deadline: January 15, 2011 - February 15, 2011
September 1, 2011 - October 1, 2011

Emerging Frontiers in Research and Innovation 2011 (EFRI-2011) - NSF 10-596
Deadline: October 04, 2010
November 08, 2010
April 01, 2011

Strategic Technologies for CyberInfrastructure (STCI) - PD 11-7684
Deadline: March 15, 2011 - March 31, 2011

Energy, Power, and Adaptive Systems (EPAS) - PD 10-1518
Deadline: February 07, 2011 (full proposal)
April 01, 2011 (application)

Cyber-Physical Systems (CPS) - NSF 10-515
Deadline: March 21, 2011
January 17, 2012

High Performance Computing System Acquisition: Enhancing the Petascale
Computing Environment for Science and Engineering - NSF 11-511
Deadline: March 7, 2011

Communications, Circuits, and Sensing-Systems (CCSS) - PD 11-7564
Deadline: February 07, 2011 (Letter of Intent)
October 07, 2011 (Full Proposal)

Back to Contents

Call for Demonstrations: ACM/SIGDA University Booth at DAC

Call for Demonstration

24th ACM SIGDA University Booth
at the 48th Design Automation Conference
San Diego Convention Center
San Diego, California
June 5-10, 2011

This year marks the 24th University Booth at the Design Automation
Conference. The booth is an opportunity for university researchers to
display their results and to interact with participants at
DAC. Presenters and attendees at DAC are especially encouraged to
participate, but participation is open to all members of the
university community. The demonstrations include new EDA tools, EDA
tool applications, design projects, and instructional materials.

* The university booth will be located near the technical sessions for
improved visibility.

* The university booth will be open two full days. June 7th - 8th:
10am - 5pm.

* The submission is in a 5-min video presentation format. Live
demonstrations performed at the booth by university researchers
simultaneous with the video presentations. Submitted video are
considered for publications in the ACM Digital Library. Also, it
will be featured on the DAC and SIGDA web pages, and be available

* Participants at the University Booth are also provided with modest
travel grant reimbursements, provided that posters are hung for the
entire duration of the conference and that demonstrations are
completed during the time slots that they are
scheduled. Participants who receive funding for the conference via
alternative sources such as the Ph.D. forum and Student Design
Contest are not eligible for travel grants through the University

Tentative Deadline for registration is May 2, 2011

To apply for participation, please visit the University Booth website
( ) Video demonstrations should
include a brief title sequence identifying the name of the research
group and university, the team members, and stating "SIGDA University
Booth at DAC 2011". Otherwise, there is complete freedom in how a
group wishes to present their work. A sample video is available on
Youtube ( )

Booth Coordinators

Naehyuck Chang (
Baris Taskin (
Joe Zambreno (

Back to Contents

Call for Papers: IEEE/ACM International Symposium on Low Power Electronics and Design

Call for Papers
ISLPED 2011 (

Location: Fukuoka, Japan
Date: August 1-3, 2011

Technical paper submission deadline: March 7, 2011
Notification of paper acceptance: April 29, 2011
Camera-ready version due: May 25, 2011

The International Symposium on Low Power Electronics and Design (ISLPED)
is the premier forum for presentation of recent advances in all aspects
of low power design and technologies, ranging from process and circuit
technologies, simulation and synthesis tools, to system level design and
optimization. Specific topics include, but are not limited to, the
following two main areas, each with three sub-areas:

1. Architecture, Circuits, and Technology
1.1. Technologies and Digital Circuits
1.2. Logic and Microarchitecture Design
1.3. Analog, MEMS, Mixed Signal and Imaging Electronics

2. Design Tools, System and Software Design
2.1. CAD & Design Tools
2.2. System Design and Methodologies
2.3. Software Design and Optimization


Submissions should be full-length papers of up to 6 pages (double-column
format, font size 9pt to 10pt), including all illustrations, tables,
references and an abstract of no more than 100 words. Papers exceeding
the six-page limit will not be reviewed. Electronic submission in pdf
format only via the web is required. More information on electronic
submission to ISLPED’11 can be found at


General Co-Chairs
-Naehyuck Chang, Seoul National Univ.
-Hiroshi Nakamura, The Univ. of Tokyo

TPC Co-Chairs
-Kenichi Osada, Hitachi
-Massimo Poncino, Politecnico Di Torino

Vice General Chair
-Koji Inoue, Kyushu Univ.

Local Arrangement Chair
-Hiroaki Honda, ISIT

-Tohru Ishihara, Kyushu Univ.
-Yuan Xie, Penn State Univ.

Special Session Co-Chairs
-Toshinori Sato, Fukuoka Univ.
-Youngsoo Shin, KAIST

Registration Chair
-Hiroyuki Tomiyama, Ritsumeikan University

Publicity Co-Chairs
-Jian-Jia Chen, Karlsruhe Institute of Tech.
-Hamid Mahmoodi, San Francisco State Univ.
-Yu Wang, Tsinghua Univ.

Design Contest Co-Chairs
-Chia-Lin Yang, National Taiwan Univ.
-Yiran Chen, University of Pittsburgh

Exhibits Co-Chairs
-Satoshi Goto, Waseda Univ.
-Masaaki Kondo, The Univ. of Electro-Communications

Publication Co-chairs
-Masanori Hashimoto, Osaka Univ.
-Taewhan Kim, Seoul National Univ.

Web Chair
-Pai Chou, UC Irvine and National Tsing Hua Univ.

Industry Liaison
-Kunio Uchiyama, Hitachi
-Sungjoo Yoo, POSTEC

-Kiyoung Choi (Seoul National University)
-Takayasu Sakurai (The University of Tokyo)
-Hiroto Yasuura (Kyushu University)

Back to Contents

Call for Papers: Workshop on Green Multimedia Communication

Workshop on Green Multimedia Communication

This workshop will be held with IEEE International Conference on
Multimedia and Expo, Barcelona, Spain, July 2011.

Goals: To establish a forum for sharing the latest progress in
developing energy-conservation techniques for multimedia

Significant amounts of energy may be consumed for the production,
storage, transmission, reception, and consumption of multimedia
content. Many techniques have been proposed to reduce the energy
consumption of multimedia communication, from efficient network
protocols to better compression algorithms, from adjusting display’s
brightness to reducing frame rates. The workshop provides a forum in
which researchers can discuss ideas about the recent progress in green
multimedia communication.


Topics of interest related to this workshop include but are not limited to:

* principles for designing technologies for energy-efficient
multimedia communication

* energy conservation techniques for production, storage,
transmission, reception, and consumption

* energy-efficient networking protocols or communication
algorithms for multimedia content delivery

* energy-efficient servers for multimedia streaming

* requirements to fairly and objectively evaluate energy-saving

* multimedia content as benchmarks

* metrics to evaluate multimedia quality when energy-conservation
techniques are applied

* tools (hardware, software, or both) that can quantify energy
savings for multimedia content production, storage, delivery,
and display

* algorithms for energy management in office, computer labs to
handle efficient mechanisms to reduce power consumption in
multimedia activities.

* Intelligent ambient systems to schedule multimedia communication
based on limited resources

This workshop especially welcomes submissions of data, tools, and
programs that can be publicly available to other
researchers. Contributors are encouraged to provide live demonstration
in the workshop.

Important Dates

Submission: February 20, 2011

Notification to authors: April 10, 2011

Final version: April 20, 2011

Submission Instructions

Submitted papers must be no longer than eight 8.5" x 11" pages,
including figures, tables, and references; two-column format, using
10-point type on 12-point (single-spaced) leading; and a text block
6.5" wide x 9" deep. Author names and affiliations should appear on
the title page. Papers must be in PDF and submitted on-line through
the ICME web site.

Simultaneous submission of the same work to multiple venues,
submission of previously published work, or plagiarism constitutes
dishonesty or fraud. IEEE, like other scientific and technical
conferences and journals, prohibits these practices and may take
action against authors who have committed them. Author Guidelines.

General Co-Chairs

Yung-Hsiang Lu, Purdue,
Yung Yi, KAIST,
Priya Mahadevan, PARC,

Organized by the Green Multimedia Communication Interest Group of the
IEEE Multimedia Communication Committee

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Call for Papers: IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2011)

IEEE/ACM International Workshop on System-Level Interconnect Prediction
(SLIP 2011)

The 2011 System Level Interconnect Prediction (SLIP) workshop will be
co-located with the 48th IEEE/ACM Design Automation Conference on June 5,
2011 at the Convention Center, San Diego, CA. The general technical scope of
the workshop is the design, analysis and prediction of intercommunication
fabrics in electronic systems. The organizing committee invites original
contributions to the workshop. These contributions include papers,
tutorials, panels, and special sessions. Regular papers will be double blind
reviewed. Submissions with author information will be rejected. We accept
papers based on novelty and contributions. IEEE will hold the copyright for
SLIP 2011 proceedings. Authors of accepted papers must sign an IEEE
copyright release form for their papers.

Representative technical topics include, but are not limited to:
1. Interconnect prediction and optimization at various IC design stages
2. Interconnect design challenges and system-level NoC design
3. Design and analysis of power and clock networks
4. Interconnect architecture of structural designs and FPGAs
5. Interconnect fabrics of many-core architectures
6. Design-for-manufacturing (DFM) techniques for interconnects
7. High speed chip-to-chip interconnect design
8. Design and analysis of chip-package interfaces
9. Interconnect topologies of multiprocessor systems
10. 3D interconnect design and prediction, including TSV architecture and
monolithic 3D stacking
11. Emerging interconnect technologies, e.g., RF interconnects, photonic
networks, carbon-based interconnects, etc.
12. Synergies between chip intercommunication networks and networks arising
in other contexts such as social networks, system biology, etc.

Important dates:
Abstract Registration Due: Mar. 4, 2011
Submission Deadline: Mar. 11, 2011
Notification Due: Apr. 1, 2011
Final Version Due: Apr. 15, 2011

Authors are invited to electronically submit papers of up to 8 pages,
double-columned, 9pt or 10pt font in IEEE proceedings format by following
the instructions at The
proceedings of SLIP 2011 will be published by IEEE Press. More details about
SLIP 2011, including submission guidelines, travel funding sources, and
travel information can be found online at:

General Chair: Janet Wang, Univ. of Arizona, USA
Technical Program Chair: Deming Chen, Univ. of Illinois, USA
Publicity Chair: Rasit O. Topaloglu, GLOBALFOUNFDRIES Inc., USA
Finance Chair: Mustafa Ozdal, Intel, USA
Local Arrangements Chair: Andrew B. Kahng, UC San Diego, USA
Publication Chair: Chen Dong, Magma, USA

Steering Committee Members:
Chung-Kuan Cheng, University of California at San Diego, USA
Giovanni De Michelli, Ecole Polytechnique Federale de Lausanne, Switzerland
Andrew B. Kahng, University of California at San Diego, USA
Paul Kohl, Georgia Institute of Technology, USA
Sherief Reda, Brown University, USA,

Program Committee Members
Yu (Kevin) Cao, Arizona State University, USA
Chung-Kuan Cheng, University of California, San Diego, USA
Deming Chen, University of Illinois, USA
Chris Chu, Iowa State University, USA
Chen Dong, Magma Design Automation, USA
Matthew Guthaus, University of California, Santa Cruz, USA
Tsung-Yi Ho, National Cheng Kung University, Taiwan
Hui-Ru Jiang, National Chiao Tung University, Taiwan
Andrew B. Kahng, University of California, San Diego, USA
Bin Li, IBM, USA
Zhuo Li, IBM, USA
Jens Lienig, Dresden University of Technology, Germany
John Lillis, University of Illinois, Chicago, USA
Sung Kyu Lim, Georgia Institute of Technology, USA
Igor Markov, University of Michigan, USA
Mustafa Ozdal, Intel, USA
David Z. Pan, UT Austin, USA
Sherief Reda, Brown University, USA
Jarrod Roy, IBM, USA
Prashant Saxena, Synopsys, USA
Dirk Stroobandt, Ghent University, Belgium
Rasit O. Topaloglu, GLOBALFOUNDRIES, Milpitas, USA
Janet Wang, University of Arizona, USA
Payman Zarkesh-Ha, University of New Mexico, USA

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Call for Papers: ACM Journal on Emerging Technologies in Computing Systems Special Issue on Asynchrony in System Design

ACM Journal on Emerging Technologies in Computing Systems
Special Issue on Asynchrony in System Design

DEADLINE: March 15, 2011 (note new deadline)

Authors are invited to submit papers for a special issue of the ACM
Journal on Emerging Technologies in Computing Systems (JETC) on
asynchronous design. The journal provides comprehensive coverage of
innovative work in the specification, design, analysis, simulation,
verification, testing, and evaluation of computing systems constructed
out of emerging technologies. JETC topic areas include computing and
sensing devices and systems built using microelectromechanical,
biological/biochemical, nanoscale electronic, asynchronous, and
quantum technologies.

This special issue will focus on asynchrony in system design. Papers
are solicited on any aspect of asynchronous design, ranging from the
core topics of design, synthesis, analysis and test, to new
asynchronous applications in emerging computing technologies. Topics
of interest include, but are not limited to:

- Asynchrony in emerging technologies, including bio, nano, optical and quantum
- Asynchronous variability-tolerant design and design for manufacturing
- Asynchronous power-adaptive and energy-harvesting systems
- Asynchronous on-chip networks
- Elastic and latency-tolerant synchronous and GALS systems
- CAD tools for asynchronous design, analysis, optimization and test
- Physical design of clockless and mixed-timing systems
- Reliability, security, and radiation tolerance in asynchronous systems
- Formal methods for concurrent system analysis and verification

Information about JETC, including instructions for manuscript
preparation, is available at Please submit your
manuscript electronically at, and
indicate "Special Issue on Asynchrony in System Design" on the cover
page and in the notes section of the submission form. Manuscripts
must conform to the JETC style (double-spaced in 10-point font), and
be limited to 20 pages for research papers, and 40-50 pages for
tutorial and survey papers.

Expanded versions of previously published conference research papers
are welcome as long as they contain at least 30% new material; authors
should clearly state in a footnote on the first page how the
manuscript differs from the conference paper. Papers simultaneously
submitted elsewhere may be returned without review.

Please contact the guest editors with any questions, and visit for up-to-date information.


Submission Deadline: Mar 15, 2011
Author Notification: Jun 1, 2011
Revised Manuscripts Due: Jul 1, 2011
Notice of Final Acceptance: Aug 15, 2011
Final Manuscripts Due: Oct 1, 2011
Publication Date: December 2011


Prof. Montek Singh
Dept. of Computer Science
Univ. of North Carolina at Chapel Hill

Prof. Steven M. Nowick
Dept. of Computer Science
Columbia University

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Design Contest: 11th International Low Power Design Contest


11th International Low Power Design Contest
Location: Fukuoka, Japan
Date: August 1-3, 2011

Submission deadline: 11:59PM Pacific Daylight Time, May 27th, 2011.

The International Symposium on Low Power Electronics and Design
(ISLPED) is holding the International Low Power Design Contest to
provide a forum for universities to showcase original "power-aware"
designs and to highlight the innovations and design choices targeted
at low power. The goal is to encourage and highlight design-oriented
approaches to power reduction.

The best designs will be selected and invited for presentation at
ISLPED 2011. A special session in the symposium will be devoted to the
Low Power Design Contest.

An industry-sponsored cash award will be awarded to each selected
design entry (up to 5 entries may be selected). The prize money is
typically enough to cover the conference registration fee and travel
expenses for the speaker.

The deadline for submissions is 11:59PM Pacific Daylight Time, May
27th, 2011. The manuscript and a cover page (must be in separate PDF
files) should be submitted electronically to both Design Contest
Chairs. The author name(s) and affiliation(s) must be omitted in the
main manuscript for blind review. Acceptance and rejection notices
will be emailed to the contact author in late June. More information
on design contest submission can be found at

Design Contest Co-Chairs

Chia-Lin Yang
Dept. of CSIE
National Taiwan University
Taipei 10617

Yiran Chen
Dept. of EE
University of Pittsburgh
Pittsburgh, PA 15261

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