SIGDA E-News 1 May 2011, Vol. 41, No. 5

1 May 2011 :: ACM/SIGDA E-NEWSLETTER :: Vol. 41, No. 5
 Special Interest Group on Design Automation
1 May 2011, Vol. 41, No. 5 Online archive:
SIGDA News     Contributing author: Marc Riedel <>     Contributing author: Matthew Guthaus <> What is Flexible Electronics?     Contributing authors: Kwang-Ting (Tim) Cheng and Tsung-Ching Huang     University of California, Santa Barbara     From: Mehmet Yildiz <> Paper Submission Deadlines     From: Debjit Sinha <> Upcoming Conferences and Symposia     From: Debjit Sinha <> Upcoming Funding Opportunities     From: Sudeep Pasricha <> Final Call for Demonstrations: 24th ACM SIGDA University Booth at the 48th Design Automation Conference     From: Naehyuck Chang <> Call for Papers: International Symposium on Electronic System Design (ISED) 2011     From: M. Gomathisankaran <> Call for Papers: Journal of ECE Special Issue on ESL Design Methodology     From: Deming Chen <> Call for Papers: The First International IEEE Workshop on Thermal Modeling and Management: Chips to Data Centers     From: Sherief Reda <> Call for Participation: System Level Interconnect Prediction 2011     From: Deming Chen <> Call for Papers: Journal of ECE Special Issue on on Energy and Thermal Management of Embedded Computing     From: Qinru Qiu <> Call for Papers: Special Issue on Probabilistic Embedded Computing     From: Vincent Mooney <>
Comments from the Editors
Dear ACM/SIGDA members, The "What is" column is looking for articles about new developments which the EDA community would like to hear about. We think that many of you are working on new and exciting products, so if you are interested in sharing your ideas please contact Mehmet Yildiz <>. An article only needs to be about 1 page long with several references. We think your contribution would be very beneficial to the community. All articles are included in the ACM digital library and there is no restriction for the reproduction of the article for printed publication later on. In this issue, we reprinted an old article on "What is Flexible Electronics?". Matthew Guthaus, E-Newsletter Editor; Marc Riedel, E-Newsletter Associate Editor; Debjit Sinha, E-Newsletter Associate Editor; Lin Yuan, E-Newsletter Associate Editor; Umit Y Ogras, E-Newsletter Associate Editor; Sudeep Pasricha, E-Newsletter Associate Editor; Mehmet Yildiz, E-Newsletter Associate Editor; Srinivas Katkoori, E-Newsletter Associate Editor
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Mentor dismisses Icahn's board nominees EDA vendor Mentor Graphics Corp. Monday (April 25) fired back at billionaire financier Carl Icahn, saying that Icahn is distorting the qualifications of his three nominees to Mentor's board of directors and exaggerating their relevance to the work Mentor does. UC Berkeley, Lawrence Berkeley Lab start Synthetic Biology Institute A new institute formed by the University of California, Berkeley, and Lawrence Berkeley National Laboratory will work to engineer cells and biological systems to tap discoveries in health, energy and new materials, among other targets. Agilent Technologies Inc. is the first corporate partner. Reducing Risk, Cost and Time to Market Chip vendors or module manufacturers wanting to manufacture an SoC know that volumes of one to two million chips per year are required to make the venture feasible. A chip vendor wanting to develop a radio would have to determine the opportunity for the parts and perform a return on investment calculation. Often, the up-front investment doesn't justify the savings, usually because of insufficient volume, lead time to production and risk due to complexity. Peter Thiel: We$-1òùre in a Bubble and Itòùs Not the Internet. Itòùs Higher Education.-A Paypal co-founder, hedge fund manager and venture capitalist Peter Thiel starts a social experiment by funding students to "drop out" of college. Texas Instruments acquires National Semiconductor Corporation Texas Instruments(TXN) sees its $6.5 billion acquisition of National Semiconductor(NSM) as a launch pad for selling analog chips into a vast array of everyday electrical devices, according to the company's CFO Kevin March.
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What is Flexible Electronics?
Kwang-Ting (Tim) Cheng and Tsung-Ching Huang University of California, Santa Barbara Flexible electronics has recently attracted much attention because of their potential in providing cost-efficient solutions to large-area applications such as rollable displays and TVs, e-paper, smart sensors and transparent RFIDs. The key advantages of flexible electronics, compared with current silicon technologies, are low-cost manufacturing (e.g. ink-jet printing and roll-to-roll imprinting) and inexpensive flexible substrates (e.g. plastics). These advantages make flexible electronics an attractive candidate for next-generation consumer products which require lightweight, bendable, portable, and low-cost electronics. (1) Key Element. Thin-film transistors (TFTs) are key elements to implement flexible circuits because of their compatibility with flexible substrates and low-cost manufacturing methods. TFTs can be categorized as a) inorganic and b) organic TFTs, depending on the material used for the semiconducting layer. Typical inorganic TFTs include a-Si:H and metal-oxide TFTs, while organic TFTs utilize various organic materials such as Pentacene, PQT-12, and F8T2. Inorganic TFTs usually exhibit higher long-term reliability and carrier mobility, while organic TFTs can be manufactured under room temperature with a much lower capital investment in circuit-printing facilities. (2) Integration. In principle, flexible electronics is ideal for integration. Compared with conventional microelectronics, flexible electronics does not require extrinsic packages such as ceramics. Instead, flexible circuits and packages can be manufactured and integrated together using only plastics. To further integrate displays and circuits, functional .inks. can be applied onto different layers for both flexible circuits and displays manufacturing. These layers can then be stacked together to complete the flexible electronic systems. Furthermore, thanks to the flexible substrates, flexible electronic systems can be easily attached to virtually any surfaces and even made invisible, if particularly TFT technologies such as metal- oxide TFTs are used. (3) The Future. Flexible electronics is still in its early stage and requires years to reach maturity. The major roadblocks such as poor air-stability and low carrier mobility have been mitigated significantly in recent years. However, there are still lack of modeling, analysis and simulation tools to support design for flexible electronics. The real challenge to come, however, is to find its killer applications that current semiconductor and LCD-display technologies cannot achieve. Recent advances in thin-film technologies such as solar cell, battery, active and passive elements have made flexible electronics from a scientific fiction to a reachable reality, despite that it is still a far one. To read more about flexible electronics, see. E. Cantotore, et al, "A 13.56-MHz RFID System Based on Organic Transponders," IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 1, pp. 84-92, Jan. 2007. K. Myny, et al, "An Inductively-Coupled 64b Organic RFID Tag Operating at 13.56MHz with a Data Rate of 787b/s," IEEE Proc. of International Solid-State Circuit Conference (ISSCC), pp. 290-291, Feb. 2008. V. Subramanian et al., "Printed Electronic Nose Vapor Sensors for Consumer Product Monitoring," IEEE Proc. International Solid-State Circuit Conference (ISSCC), pp.1052-1059, Feb. 2006. M. Takamiya et al., "Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches," IEEE Proc. International Solid-State Circuit Conference (ISSCC), pp. 362-363, Feb. 2007. L. Liu et al., "A 107pJ/b 100Kb/s 0.18um Capacitive-Coupling Transceiver for Printable Communication Sheet," IEEE Proc. International Solid-State Circuit Conference (ISSCC), pp. 292-293, Feb. 2008. H. Kawaguchi et al., "Cut-and-Paste Customization of Organic FET Integrated Circuit and Its Application to Electronic Artificial Skin," IEEE Journal of Solid-State Circuits (JSSC), vol. 40, no. 1, pp. 177-185, Jan. 2005. S.H. Kwon et al., "Flexible Paper-Like Display Using Charged Polymer Particles," Proc. Society for Information Display (SID), pp. 1838-1840, May 2006. H. Klauk et al., "Ultralow-Power Organic Complementary Circuits," Nature, vol. 445, Feb. 2007. T.-C. Huang and K.-T. Cheng, "Design for Printability for Flexible Electronics," International Symposium for Flexible Electronics and Display (ISFED), Dec. 17-18, 2007. T-C. Huang, H-Y. Tseng, C.-P. Kung, and K-T. Cheng, "Reliability Analysis for Flexible Electronics: Case Study of a-Si:H TFT Scan Driver," IEEE/ACM Design Automation Conference (DAC), pp. 966-969, San Diego, June 4-8, 2007.
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Paper Submission Deadlines
HiPC'11 - Int'l Conference on High Performance Computing Bangalore, India Dec 18-21, 2011 Deadline: May 16, 2011 MICRO'11 - Int'l Symposium on Microarchitecture Porto Alegre, Brazil Dec 3-7, 2011 Deadline: May 25, 2011 BodyNets'11 $-1òó Intòùl Conference on Body Area Networks-A Beijing, China Nov 7-10, 2011 Deadline: May 31, 2011 ICFPT'11 - Int'l Conference on Field-Programmable Technology Delhi, India Dec 12-14, 2011 Deadline: Jun 8, 2011 HLDVT$-1òù11 òó Intòùl High-Level Design, Validation and Test Workshop-A Napa Valley, CA Nov 9-11, 2011 Deadline: Jun 10, 2011 BIOCAS'11 - Biomedical Circuits and Systems Conference San Diego, CA Nov 10-12, 2011 Deadline: Jun 10, 2011 ISED$-1òù11 òó Intòùl Symposium on Electronic System Design -A (co-located with Int$-1òùl Workshop on Embedded Computing and Communication)-A Kochi, India Dec 19-21, 2011 Deadline: Jun 15, 2011 ICPADS'11 - Int'l Conference on Parallel and Distributed Systems Tainan, Taiwan Dec 7-9, 2011 Deadline: Jun 24, 2011 ASP-DAC'11 - Asia and South Pacific Design Automation Conference Sydney, Australia Jan 30 - Feb 2, 2012 Deadline: Jul 19, 2011
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Upcoming Conferences and Symposia
ISCAS'11 - Int'l Symposium on Circuits and Systems Rio De Janerio, Brazil May 15-18, 2011 ISCA$-1òù11 òó Intòùl Symposium Computer Architecture-A San Jose, CA Jun 4-8, 2011 SLIP$-1òù11 - System Level Interconnect Prediction-A San Diego, CA June 5, 2011 DAC$-1òù11 òó Design Automation Conference-A San Diego, CA Jun 5-10, 2011 SASP$-1òù11 òó Symposium on Application Specific Processors -A (co-located with DAC$-1òù11)-A San Diego, CA Jun 5-6, 2011 AHS$-1òù11 - NASA/ESA Conference on Adaptive Hardware and Systems-A (co-located with DAC$-1òù11)-A Jun 6-9, 2011 San Diego, CA MSE'11 - Microelectronics Systems Education San Diego, CA (co-located with DAC$-1òù11)-A Jun 5-6, 2011 24th ACM SIGDA University Booth (co-located with DAC$-1òù11)-A San Diego, CA Jun 5-10, 2011 DFM&Y'11 - Int'l Workshop on Design for Manufacturability & Yield San Diego, CA (Co-located with DAC) Jun 6, 2011 IWBDA'11 - Int'l Workshop on Bio-Design Automation San Diego, CA (Co-located with DAC) Jun 6-7, 2011 MEMOCODE'11 $-1òó Intòùl Conference on Formal Methods and Models for Codesign-A Cambridge, United Kingdom Jul 11-13, 2011 ASQED'11 - Asia Symposium on Quality Electronic Design Kuala Lumpur, Malaysia Jul 19-20, 2011 ETMEC'11 - Int'l Workshop on Energy and Thermal Management of Embedded Computing Maui, Hawaii Jul 31 - Aug 4, 2011 VLSI-SoC$-1òù11 òó Intòùl Conference on Very Large Scale Integration and System on Chip-A Hong Kong, China Oct 3-5, 2011 PACT'11 - Int'l Conference on Parallel Architectures and Compilation Techniques Galveston Island, TX Oct 8-12, 2011 ESWEEK'11 - Embedded Systems Week (CASES, CODES+ISSS, and EMSOFT) Taipei, Taiwan Oct 9-14, 2011 Wireless Health$-1òù11-A San Diego, CA Oct 10-13, 2011 ICCAD$-1òù11 òó Intòùl Conference on Computer-Aided Design-A San Jose, CA Nov 6-10, 2011
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Upcoming Funding Opportunities
ASEE Office of Naval Research (ONR) Sabbatical Leave Program Deadline: N/A Naval Research Laboratory (NRL) Postdoctoral Fellowship Program Deadline: Continuous DARPA Microsystems Technology Office-Wide Broad Agency Announcement - DARPA-BAA-10-35 Deadline: Continuous DOD ARL/ARO Core Broad Agency Announcement for Basic and Applied Scientific Research for Fiscal Years 2007 through 2011 (W911NF-07-R-0001) Deadline: Continuous through September 30, 2011 Robust Computational Intelligence - AFOSR-BAA-2010-01 Deadline: Continuous Systems and Software - AFOSR-BAA-2010-01 Deadline: Continuous ERDC BAA - Computational Science and Engineering (ITL-1) Deadline: Continuous Advanced Distributed Sensor Technologies - BAA 57-09-06 Deadline: Continuous Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01) Deadline: Continuous High Performance Computing on Massively Parallel Architectures (BAA 64-09-01) Deadline: Continuous ASEE-NRL Postdoctoral Fellowship Program Deadline: N/A DOE Postdoctoral Appointments Deadline: N/A Sabbaticals and Faculty Appointments Deadline: continuous McDonnell Foundation Studying Complex Systems - 21st Century Science Collaborative Activity Awards Deadline: continuous NSF Expeditions in Computing $-1òó NSF 10-564-A Deadline: May 10, 2011 Research Coordination Networks (RCN) $-1òó NSF 11-531-A Engineering and Education for Sustainability (RCN-SEES) track Deadline: May 24, 2011 Cyberlearning: Transforming Education $-1òó NSF 10-620-A Deadline Date: May 14, 2011 (letter of intent) Science and Technology Centers: Integrative Partnerships $-1òó NSF 11-522-A Preliminary Proposal Deadline Date: May 30, 2011 Full Proposal Deadline Date: February 3, 2012 Industry/University Cooperative Research Centers Program (I/UCRC) $-1òó NSF 10-595-A Letter of Intent Deadline Date: June 26, 2011 Full Proposal Deadline Date: September 26, 2011 Faculty Early Career Development (CAREER) Program $-1òó NSF 11-690-A Full Proposal Deadline Date: July 25, 2011 (BIO, CISE, EHR, OCI) Full Proposal Deadline Date: July 26, 2011 (ENG) SRC Research in Back End Processes, Packaging, and Interface Deadline (white paper): Wednesday, May 4, 2011
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Final Call for Demonstrations: 24th ACM SIGDA University Booth at the 48th Design Automation Conference
Final Call for Demonstrations 24th ACM SIGDA University Booth at the 48th Design Automation Conference San Diego Convention Center San Diego, California, June 5-10, 2011 This year marks the 24th University Booth at the Design Automation Conference. The booth is an opportunity for university researchers to display their results and to interact with participants at DAC. Presenters and attendees at DAC are especially encouraged to participate, but participation is open to all members of the university community. The demonstrations include new EDA tools, EDA tool applications, design projects, and instructional materials. * The university booth will be open two full days. June 7th - 8th: 10am - 5pm. * The submission is in a 5-min video presentation format. Live demonstrations performed at the booth by university researchers simultaneous with the video presentations. Submitted videos are considered for publication in the ACM Digital Library. Also, it will be featured on the DAC and SIGDA web pages, and be available year-round. * Submission is made online. Upload a single PDF file with the title, list of authors and their affiliations, abstract, and YouTube link to the online video presentation. You can optionally attach a supporting paper. * Participants at the University Booth are also provided with modest travel grant reimbursements, provided that posters are hung for the entire duration of the conference and that demonstrations are completed during the time slots that they are scheduled. Participants who receive funding for the conference via alternative sources such as the Ph.D. forum and Student Design Contest are not eligible for travel grants through the University Booth. Submission deadline: May 4, 2011 11:59 PM PDT (This deadline is firm) Acceptance notification: May 7, 2011 Submission site: To apply for participation, please visit the University Booth website ( Video demonstrations should include a brief title sequence identifying the name of the research group and university, the team members, and stating "SIGDA University Booth at DAC 2011". Otherwise, there is complete freedom in how a group wishes to present their work. A sample video is available on Youtube ( Booth Coordinators Naehyuck Chang ( Baris Taskin ( Joe Zambreno (
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Call for Papers: International Symposium on Electronic System Design (ISED) 2011
CALL FOR PAPERS International Symposium on Electronic System Design (ISED) 2011 (19-21 December 2011, Kochi, India) IMPORTANT DATES Manuscript submission : 15th June 2011 Notifications of review status : 15th August 2011 Camera ready papers : 15th September 2011 Symposium : 19-21 December 2011 MORE INFORMATION ABOUT THE SYMPOSIUM When we think about one single thing that has caused maximum social impact, the "mobile phone" comes to our mind. Mobile phones and other similar systems are essentially embedded systems designed using system-on-chip (SoC) technology. This system consists of several heterogeneous components, such as: (1) analog/mixed signal circuits including radio frequency (RF) components, (2) digital circuits, (3) power management systems, including the battery, and (4) software. The objective of the International Symposium on Electronic System Design (ISED) is to bring experts from these fields together so that efficient design of such portable systems is made possible. The next issue that arises, is how to train the next generation of engineers to acquire the needed expertise. Thus, in conjunction with ISED, the Workshop for Engineering Scholars (WES) is organized. The proceedings of the ISED is published by the IEEE Computer Society Conference Publishing Services and hence is archived in the digital libraries (CSDL, IEEE Xplore, IEEE IEL). The highlights of first of its series ISED 2010 are: NSF-USA and DST-India fundings, 17 Keynote/Plenary/Invited talks, 41 contributing papers, IEEE technical co-sponsorship, and a special issue in ACM JETC. ISED 2011 will continue the same momentum. SYMPOSIUM TRACKS ISED 2011 will have the following tracks: (1) Analog/Mixed-Signal System Design (AMS) (2) Digital System Design and Validation (DSD) (3) Embedded System Design (ESD) (4) Emerging Technology and System Design (ETD) (5) Power Aware System Design (PSD) (6) Software System and Application Design (SSD) (7) Workshop for Engineering Scholars (WES) MANUSCRIPT INFORMATION Manuscripts reporting high quality original and unpublished research are solicited for this symposium. The manuscripts will undergo double-blind review by a strong team of reviewers and program committee members consisting of leading researchers from around the globe. All accepted papers will appear in the symposium proceedings to be published by the IEEE-CS Conference Publishing Services (IEEE-CPS) provided at least one of the authors of each paper registers for the symposium at full rate. The extended versions of selected papers will be considered for possible publication in a journal. SUBMISSION INFORMATION A single-spaced, double-column, (maximum) 6-page, IEEE-CS format manuscript should be submitted as a single pdf file using the following link: For more information visit:
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Call for Papers: Journal of ECE Special Issue on ESL Design Methodology
Journal of Electrical and Computer Engineering Special Issue on ESL Design Methodology ESL (electronic system-level) design is an emerging design methodology that allows designers to work at higher levels of abstraction than typically supported by register transfer level (RTL) descriptions. Its growth has been driven by the continuing complexity of IC design, the shortening time to market and growing number of design constraints and objectives, which have made RTL implementation less efficient. ESL methodology holds the promise of dramatically improving design productivity by accepting designs written in high-level languages such as C, SystemC, C++, and MATLAB, etc. and implementing the function straight into hardware. Designers can also leverage ESL to optimize performance and power by converting compute intensive functions into customized cores in SoC designs or FPGAs. It can also support early embedded-software development, architectural modeling, and functional verification. ESL has been predicted to grow in both user base and revenue steadily in the coming decade. Meanwhile, the design challenges in ESL remain. Some important research challenges include effective hardware/software partitioning and co-design, high-quality high-level synthesis, seamless system IP integration, accurate and fast performance/power modeling, and efficient debugging and verification, etc. Research topics of interest for this special issue include, but are not limited to: * New algorithmic development for high-level synthesis * Domain-specific high-level synthesis (DSP, processor-based, control-intensive, etc.) * High-level synthesis for emerging technologies (3D, biochips, nanoscale circuits, etc.) * Extensible/reconfigurable processor synthesis * ESL design space exploration * Virtual prototyping * Transaction Level Modeling * Hardware/software partitioning and co-design * Hardware/software interaction and interface * ESL-to-RTL verification * ESL debugging * ESL power/performance analysis * ESL-IP integration * ESL for FPGAs * ESL and embedded-software development * Design case studies with ESL Before submission authors should carefully read over the journal's Author Guidelines, which are located at Prospective authors should submit an electronic copy of their complete manuscript through the Journal Manuscript Tracking System at according to the following timetable: Manuscript Due: July 1, 2011 First Round of Reviews: October 1, 2011 Publication Date: January 1, 2012 Lead Guest Editor: Deming Chen, University of Illinois at Urbana-Champaign, USA Guest Editors: Kiyoung Choi, Seoul National University, Korea Philippe Coussy, Lab-STICC, Université de Bretagne-Sud, France Yuan Xie, Pennsylvania State University at University Park, USA Zhiru Zhang, Xilinx Inc., USA
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Call for Papers: The First International IEEE Workshop on Thermal Modeling and Management: Chips to Data Centers
Call for Papers The First International IEEE Workshop on Thermal Modeling and Management: Chips to Data Centers Jul 25, 2011, Orlando, Florida in conjunction with IGCC Due Date: *May 9th 2011* High power densities and operating temperatures in multiprocessor systems impose a number of undesirable effects: performance degradation, reliability deterioration, high-energy costs, and physical damage leading to system failures. Recent research has shown that adverse effects of temperature can be modulated by efficient thermal monitoring, dynamic thermal management, thermally-aware architectures, temperature-aware compilation, hybrid computing fabrics, or by novel cooling technologies. Hardware and software design and runtime management methods, spanning from chips to datacenters, play an integral role in the overall thermal behavior and cooling costs. ITRS projects "Temperature Aware Design" as one of the cross-cutting design challenges for future manycore systems. The main goal of this workshop is to provide a forum for the researchers to share the most recent developments and ideas on thermal modeling and management in various layers of system design and management: hardware design, algorithms, applications and software, operating systems, middleware, and datacenter-level solutions. The topics of interest include, but are not limited to: * Thermal Modeling of Manycore / 3D Systems * Thermal Analysis of Computing and Communication Layers * Temperature Sensor Placement Algorithms * Thermally-Aware Design Flows * Thermal Management at Various Abstractions * Interconnect / TSV Role in Thermal Optimizations * Thermal Modeling of Large Scale Distributed Embedded Systems * Thermally-Aware Distributed Computing * Context-aware Thermal Management * Thermal Footprint of Datacenters * Physically Aware 3D Thermal Management * Electro-Mechanically Aware Thermal Models * Network Infrastructures for Enhanced Thermal Management * Thermally-Aware Embedded Computing Applications * Co-optimization of Cooling Energy and Computation/ Communication Energy * Variation Aware Thermal Management in Manycore / 3D Systems * Thermal Modeling and Management in Emerging Technologies * Cooling Mechanisms and Technologies in 2-1/2 D, 3D, Hybrid Cores Submission Guidelines: Prospective authors are invited to submit papers not exceeding 6 pages (4~6 pages) in length in standard IEEE two-column format for regular sessions. The IEEE template can be downloaded at: Prospective authors should submit an electronic copy of their completed manuscript through the EasyChair portal at: Selected papers from the TEMM workshop will be invited to submit as full-length papers in the special edition for Journal of Sustainable Computing: The submission and acceptance timeline is given below. Paper submission date: *NEW May 09 2011* Notification date: May 25 2011 Camera Ready papers: June 6 2011 Registration: All participants will be required to register for the IGCC'11 conference ( The registration includes access to the workshop. For any questions related to the workshop, please Workshop Co-Chairs: Dhireesha Kudithipudi, Rochester Institute of Technology, USA Qinru Qiu, Binghamton University, USA Ayse Kivilcim Coskun, Boston University, USA Publicity Chair: Sherief Reda, Brown University, USA Technical Program Committee: David Atienza, EPFL, Switzerland Jose Ayala, Compultense Univ. of Madrid, Spain Tianzhou Chen, Zhejiang University, China Siddharth Garg, University of Waterloo, Canada Kartik Gopalan, Binghamton University, USA Omer Khan, MIT, USA Eren Kursun, IBM T.J. Watson Research Center, USA Byeong Lee, Univ. of Texas San Antonio, USA Gang Quan, Florida International University, USA Emre Salman, Stony Brook University, USA Mircea Stan, University of Virginia, USA
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Call for Participation: System Level Interconnect Prediction 2011
Call for Participation System Level Interconnect Prediction (SLIP) 2011 June 5th, 2011 Co-located with DAC at San Diego Convention Center Advance Registration: By May 9th. IEEE/ACM member: $250; Non member: $315. Student IEEE/ACM member: $140; Student non member: $250. Late/Onsite Registration: After May 9th. IEEE/ACM member: $315; Non member: $390. Student IEEE/ACM member: $175; Student non member: $315. Preliminary Technical Program: Breakfast 8:00am - 8:30am Welcome Message + Keynote Speech 8:30am - 9:30am Riko Radojcic, QualComm Inc. Title: Design Eco-System for 3D Integration $-1òó an IFM Perspective-A Coffee Break 9:30am - 9:45am Session I: TSV Scaling and 3D FPGA 9:45am - 10:35am Session Chair: Sherief Reda, Brown University, USA Impact of Nano-scale Through-Silicon Vias on the Quality of Today and Future 3D IC Designs Dae Hyun Kim, Suyoun Kim and Sung Kyu Lim, Georgia Institute of Technology 9:45am-10:05am Architecture and Performance Evaluation of 3D CMOS-NEM FPGA Chen Dong*, Chen Chen+, Subhasish Mitra+, and Deming Chen*, * University of Illinois at Urbana Champaign; + Stanford University 10:05am-10:25am Discussion Panel $-1òó TBA-A 10:25am-10:35pm Coffee Break 10:35am - 10:50am Session II: Multicore and Embedded SoC Design 10:50am - 12:30pm Session Chair: Chung-Kuan Cheng, University of California at San Diego, USA (Invited Talk) Luca Benini, Università di Bologna, Italy Title: Many-core Interconnection Networks Trends: Fast, Vertical, Asynchronous 10:50am-11:20am Reducing Energy and Increasing Performance with Traffic Optimization in Many-core Systems George Bezerra, Stephanie Forrest and Payman Zarkesh-Ha, Univeristy of New Mexico 11:20am-11:40am System Interconnect Design Exploration for Embedded MPSoCs Chen-Ling Chou*, Radu Marculescu+, Umit Ogras#, Satrajit Chatterjee#, Michael Kishinevsky# and Dmitrii Loukianov#, * General Electric Inc.; + Carnegie Mellon University; # Intel Inc. 11:40am-12:00am Mobile System Considerations for SDRAM Interface Trends (short) Andrew Kahng* and Vaishnav Srinivas+, * University of California at San Diego; + QualComm Inc. 12:00am-12:15pm Discussion Panel $-1òó TBA-A 12:15pm-12:30pm Lunch 12:30pm - 1:30pm Session III: Advanced Techniques on Routing 1:30pm - 2:35pm Session Chair: Hui-Ru Jiang, National Chiao Tung University, Taiwan A SAT-Based Routing Algorithm for Cross-Referencing Biochips Ping-Hung Yuh*, Cliff Chiung-Yu Lin+, Tsung-Wei Huang#, Tsung-Yi Ho#, Chia-Ling Yang& and Yao-Wen Chang&, * TSMC; + Stanford University; # National Cheng Kung University; & National Taiwan University 1:30pm-1:50pm Interface Optimization for Improved Routability in Chip-Package-Board Co-Design (short) Tilo Meister*, Jens Lienig* and Gisbert Thomke+, * Dresden University of Technology; + IBM Deutschland Research and Development 1:50pm-2:05pm Stability and Scalability in Global Routing (short) Sung Kyu Han, Kwangok Jeong, Andrew Kahng and Jingwei Lu, University of California San Diego 2:05pm-2:20pm Discussion Panel $-1òó TBA -A 2:20pm-2:35pm Coffee Break + Poster Session 2:35pm - 3:00pm Panel: TSV-based 3D ICs: Why Does It Take So Long? 3:00pm - 4:00pm Moderator: Sung Kyu Lim, Georgia Institute of Technology, USA Panelists: Robert Patti (Tezzaron Semiconductor), Paul Franzon (North Carolina State University), etc. Coffee Break + Poster Session 4:00pm - 4:15pm Session IV: Power Network Resource Estimation and Design 4:15pm - 5:30pm Session Chair: Baris Taskin, Drexel University, USA (Invited Talk) Nagaraj NS, TI Title: Performance and Power Optimization in Sub-20nm Era 4:15pm-4:45pm Toward PDN Resource Estimation: A Law of Power Density Kwangok Jeong and Andrew Kahng, University of California, San Diego 4:45pm-5:05pm Distributed Power Network Co-Design with On-Chip Power Supplies and Decoupling Capacitors (short) Selcuk Kose and Eby G. Friedman, University of Rochester 5:05pm-5:20pm Discussion Panel $-1òó TBA -A 5:20pm-5:30pm Banquet Dinner + Banquet Plenary Talk 6:30pm - 8:30pm Chuck Alpert, IBM Title: Devil Is in the Detailed Router: Congestion Hotspot Prediction
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Call for Papers: Journal of ECE Special Issue on on Energy and Thermal Management of Embedded Computing
Journal of Electrical and Computer Engineering Special Issue on Energy and Thermal Management of Embedded Computing Call for Papers Excessive energy dissipation has become one of the limiting factors for the sustained growth of today$-1òùs embedded computing-A technology. High power consumption and power density reduce system reliability, increase energy as well as cooling cost, and cut the battery lifetime of mobile devices. Runtime energy/thermal management dynamically consolidates workload of computers, adjusts the power/performance mode of devices, and finds tradeoffs between quality of services (QoS) and energy dissipation. Those runtime management actions usually bring significant performance and energy overhead and should be chosen carefully with the consideration of the hardware and software environments, the user activities and QoS requirements, the battery efficiency, the communication protocols, and the routing algorithms. The main goal of this special issue is to provide a forum for the researchers to share the most recent developments and ideas on energy/thermal management in various areas of embedded computing, from application, OS, and middleware development to communication and network optimization.We also welcome contributions focusing on energy/thermal management of embedded systems powered by novel energy sources or utilizing innovative energy storage techniques. The topics to be covered include,but are not limited to: * Energy-/temperature-aware algorithm design * Runtime power/energy/thermal management * Energy/thermal analysis or optimization in various computing and communication layers * Energy-aware operating system kernels and modules * Energy/thermal modeling and simulation * Energy-/temperature-aware distributed computing * Ultralow energy design space-sub/near threshold computing in embedded systems * Design and optimization of embedded systems based on renewable energy * Battery-aware optimization of computing and communication * Co-optimization of cooling power and computation/ communication power * Network infrastructures for enhanced energy/thermal management * Energy-aware multicore architectures * Context-aware energy/thermal management of embedded computing * Energy footprinting of embedded computing systems * Energy/thermal workload/benchmark analysis and characterization * Experiences, case studies, and lessons learned for energy-/temperature-aware embedded computing applications Before submission authors should carefully read over the journal$-1òùs-A Author Guidelines, which are located at Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at according to the following timetable: Manuscript Due: July 15, 2011 First Round of Reviews: October 15, 2011 Publication Date: January 15, 2012 Lead Guest Editor Qinru Qiu Department of Electrical and Computer Engineering, Binghamton University, Binghamton, NY, 13902, USA; Guest Editors Ayse Kivilcim Coskun Department of Electrical and Computer Engineering, Boston University, Boston, MA, 02215, USA; Dhireesha Kudithipudi Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY 14623, USA; Song Ci Department of Computer and Electronics Engineering, University of Nebraska-Lincoln, 200B PeterKiewit Institute, Omaha, NE 68182, USA;
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Call for Papers: Special Issue on Probabilistic Embedded Computing
CALL FOR PAPERS ACM Transactions on Embedded Computing Systems Special Issue on Probabilistic Embedded Computing Moore$-1òùs Law dictates increased integration (reduced form factor) to-A reduce cost, size and weight while simultaneously reducing energy usage (which increases battery lifetimes). Multicore introduces yet another dimension requiring ever more scalable software design only limited by Amdahl's law. Business as usual $-1òó simply doing more of the-A same $-1òó will not achieve these goals. The aim of this special issue is-A to explore novel probabilistic computing technologies for current and emerging integrated systems. Design of low-power dependable chips with transistors and interconnects whose behaviors may have large statistical spread is the reality of cutting edge and future silicon technologies. In the face of these challenges, the International Technology Roadmap for Semiconductors talks about $-1òürelaxing the requirement of 100%-A correctness for devices and interconnects$-1òý as a way to continue device-A scaling, which thereby "may dramatically reduce costs of manufacturing, verification, and test. Such a paradigm shift is likely forced in any case by technology scaling, which leads to more transient and permanent failures of signals, logic values, devices, and interconnects.$-1òý One approach which has many facets is the-A so-called $-1òüprobabilistic designòý-A paradigm where erratic behaviors at the circuit level are captured in a description of probabilistic behavior for exposure to the chip architect and even the algorithm and systems software designer. The obvious next step is to relax the requirement of 100% correctness even for software design and tools as a way to increase performance, efficiency, and scalability. This special issue will explore this broad area and attempt to say what candidate solutions exist. For work that has been published previously in a workshop or conference, it is required that submissions to the special issue have at least 30% new content. Submissions that do not meet this requirement will be returned without review. Topics of interest include but are not limited to the following: * Probabilistic software design and tools * Probabilistic computing architectures * Software resilience * Hardware resilience * Probabilistic computing software (e.g., randomized algorithms) * Probabilistic computing hardware (e.g., arithmetic unit design) * Error and fault models for computing * Predictive models of future sources of error, e.g., parametric variations and noise (thermal, shot, flicker, etc.) * Error tolerance and correction approaches for probabilistic computing * Reliable computing with unreliable components The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TECS formatting requirements. The page count limit is 25. TIMETABLE: Submission due May 31, 2011 Review results: approx. July 31, 2011 Final copy deadline: approx. late September, 2011 Publication: Spring/Summer 2012 Guest Editor(s): * Christoph Kirsch, University of Salzburg * Vincent Mooney, Georgia Institute of Technology and Nanyang Technological University The above information is all available from
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