SIGDA E-News 1 January 2012, Vol. 42, No. 1

1 January 2012, Vol. 42, No. 1
Online archive: http://www.sigda.org/newsletter

SIGDA News
Contributing author: Matthew Guthaus <mrg@soe.ucsc.edu>
From: Lin Yuan <yuanl@synopsys.com>
What is Nano-Magnetic Logic?
Contributing author: Sanjukta Bhanja <bhanja@eng.usf.edu>
From: Srinivas Katkoori <katkoori@cse.usf.edu>
Paper Submission Deadlines
From: Debjit Sinha <debjitsinha@yahoo.com>
Upcoming Conferences and Symposia
From: Debjit Sinha <debjitsinha@yahoo.com>
Upcoming Funding Opportunities
From: Sudeep Pasricha <sudeep@colostate.edu>
Call for Papers: VLSI Design Journal Special Issue on New Algorithmic Techniques for EDA Problems
From: Shantanu Dutt <dutt@ece.uic.edu>
Call for Papers: International Symposium on Hardware-Oriented Security and Trust (HOST)
From: Gang Qu <gangqu@umd.edu>
Call for Papers: TCAD Special Section on Three-dimensional Integrated Circuits and Microarchitectures
From: Deming Chen <dchen@illinois.edu>
Call for Papers: International Conference on Formal Methods and Models for Codesign (MEMOCODE)
From: Luca Carloni <luca@cs.columbia.edu>
Call for Papers: International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
From: Sudeep Pasricha <sudeep@colostate.edu>

Comments from the Editors

Dear ACM/SIGDA members,

Welcome to the 2012 volume (number 42) of the ACM SIGDA E-Newsletter!
If you have call for papers, announcements, or other information that
is important for SIGDA members, please send it to one of the editors
below or by responding to the latest E-Newsletter. We typically send
out the E-Newsletter on the first of each month and require
information a few days prior to that in formatted plain text format.

We would also like to thank Marc Riedel for his years of service as a
SIGDA E-Newsletter Associate Editor. He is currently leaving the
position. If there are any SIGDA members interested in helping with
the SIGDA News column (along with Assoc. Editor Lin Yuan), please
contact the editor Matthew Guthaus <mrg@soe.ucsc.edu>.

In this issue, we have a new article on "What is Nano-Magnetic Logic?"
by Sanjukta Bhanja, University of South Florida. If you are interested
in contributing to the "What is..." column in the future, please
contact Srinivas Katkoori <katkoori@cse.usf.edu>. An article only
needs to be about 1 page long with several references. All articles
are included in the ACM digital library and there is no restriction
for the reproduction of the article for printed publication later.

Matthew Guthaus, E-Newsletter Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Sudeep Pasricha, E-Newsletter Associate Editor;
Srinivas Katkoori, E-Newsletter Associate Editor

Back to Contents

SIGDA News

"ACM Names 54 Distinguished Members for Contributions to Computing"
http://www.acm.org/news/featured/acm-distinguished-2011
ACM named its 2011 distinguished members for contributions to
computing which includes two members of SIGDA: Diana Marculescu,
Carnegie Mellon University; and Igor L. Markov, University of Michigan.

"EE Times' 20 hot technologies for 2012"
http://www.eetimes.com/electronics-news/4231126/EE-Times--20-hot-technologies-fo...
What follows is a list of 20 technologies EE Times editors think can
bring big changes, and that we will be tracking during 2012.

"10 notable blunders of 2011"
http://www.eetimes.com/electronics-news/4233545/10-notable-blunders-of-2011
For most of electronics, 2011 came in like a lion and is going out
like a lamb. Carryover from a strong bounce back year in 2010 set
markets booming in the early part of the year, but dragging
effects—chiefly macroeconomic concerns—have slowed business
considerably as the year draws to a close.

"ST claims world's first contactless wafer test"
http://www.eetimes.com/electronics-news/4233239/ST-contactless-wafer-test
European chip company STMicroelectronics NV has said it has produced
the first wafer on which the die were fully tested wirelessly and
without the use of contact probes.

"'Second Coming' of Magma Forced Synopsys to Deal"
http://confidential.eetimes.com/news-updates/4231120/-Second-Coming--of-Magma-Fo...
In the aftermath of the Synopsys-Magma deal, analysts are wondering
how long Magma co-founder and serial entrepreneur Rajeev Madhavan
(shown) will stick around. For now, Madhaven says he is content to
stay with the merged company so he can get the technology he helped
create into the hands of more chip designers.

"IEEE Names Six Fellows From Within Council on EDA Ranks"
http://www10.edacafe.com/nbc/articles/1/1042983/IEEE-Names-Six-Fellows-Within-Co...
The IEEE Council on Electronic Design Automation (CEDA) today
announced that six candidates from the Council have been appointed
Fellow of the IEEE effective January 1, 2012.

"Strain Speeds Organic Transistors"
http://spectrum.ieee.org/semiconductors/devices/strain-speeds-organic-transistor...
Big boost in charge-carrier mobility could open organic semiconductors
to new applications

"Intel Interview: Getting Beyond "Darn Good" Devices "
http://spectrum.ieee.org/tech-talk/semiconductors/devices/getting-beyond-darn-go...
For at least a few years, the 3-D transistor was hiding in plain
sight. Intel CEO Paul Otellini held up a shiny wafer full of them when
he showed off the company's 22nm SRAM at the Intel Developer Forum in
San Francisco in 2009. But it took until May this year before Intel
revealed exactly how those SRAM transistors are different from their
32nm progenitors. Unlike the traditional planar transistor, which
contains a gate spread along one side of a flat channel, Intel's
Tri-Gate (or FinFET) transistor employs a gate that is draped over
three sides of a 3-D channel, which juts out of plane like a fin.

"3-D printing meets robot design"
http://www.eetimes.com/electronics-news/4231050/3D-printing-meets-robot-design-
Though 3-D printing has generated a lot of buzz and interest in the
industry, the lack of widely available equipment has made the process
inaccessible to most regular would-be consumers. My Robot Nation from
Kodama Studios, however, could be changing that, bringing out
printable 3-D robots just in time for the holidays.

Back to Contents

What is Nano-Magnetic Logic?

Sanjukta Bhanja, University of South Floridaw
bhanja@eng.usf.edu

Computing using nanomagnets (Nano-Magnetic Logic) is a radically
different framework where coupling among nanomagnets contributes to
information propagation and computation. With proven operation at room
and extended temperatures, magnetic logic offers promise for zero
standby power and "instant on" functionality. In Nano-Magnetic Logic
(NML), basic unit of computation is a nanomagnet with dimensions and
materials such that it exhibits single domain behavior. Material and
geometric shape anisotropy can be exploited to orient the direction of
the overall, ground state (least energy) magnetization along a desired
easy-axis dimension (two possible configurations of magnetic dipole to
achieve Boolean Logic "0" and "1"). Central theme of computation:
when a computing nanomagnet is forced in its energetically hard axis
(direction of the smaller dimensions) and then released (also termed
as clocking), it aligns according to the neighboring magnets (dipolar
interaction) to attain minimum energy of the overall system.

The fabrication process differs between groups accounting for the
equipments' diversity and features. Fabrication is in general
accomplished via a standard electron beam lithography process with the
Nabity NPGS system to expose patterns on a Si wafer with a single
layer of PMMA resist. Next step is to deposit a film of ferromagnetic
material (say Permalloy) of desired thickness using Electron Beam
Evaporator. The patterns are usually analyzed and characterized by
Scanning electron microscopy. Magnetic Force Microscopy is in general
used for obtaining qualitative magnetic measurements. Experimental
demonstrations have a few common features, namely use of
rectangular/elliptic magnets, statically applying inputs to
demonstrate various input combinations, qualitative outputs through
magnetic force microscopes. So far, many stand-alone logic units are
experimentally demonstrated. Examples include majority logic [1],
wires, fan-outs [2, 3], NAND/NOR [4], coplanar cross-wires [5], seven
input majority (majority of majorities) gates [6] to name a few.

One of the few open problems in NML is clocking which refers to
systematic ordering of magnets. A few works in clocking revolves
around spatially moving field [7, 8, 9]. There is a handful of
experimental demonstration of input/output [2, 10]. Recently,
multi-layer magnetic cell is proposed [11] and experimentally
demonstrated [6] that promises the use of spin torque for writing and
tunnel magneto-resistance for reading. Other directions in magnetic
logic are all-spin logic [12, 14]. Key issues that need further
research are experimental demonstration [12] and cascading [14]. With
the promise of excellent CMOS integration [15], systemic architecture
framework [13] and high-speed strain-based clocking [16], NML offers
excellent competition for beyond-CMOS radiation-hardened,
adverse-temperature logic-in-memory architecture as well as
unconventional non-Boolean problem mapping, namely energy-minimization
based computer vision problems [17,18].

References:

[1] A. Imre, G. Csaba, L. Ji, A. Orlov, G. Bernstein and W. Porod,
"Majority Logic Gate for Magnetic Quantum-Dot Cellular Automata,"
Science, vol. 311, no. 5758, 2006.

[2] A. Orlov, A. Imre, G. Csaba, L. Ji, W. Porod and G. Bernstein,
"Magnetic Quantum-Dot Cellular Automata: Recent Developments and
Prospects," Journal of Nanoelectronics and Optoelectronics, vol. 3,
no. 1, pp. 55-68, 2008.

[3] J. Pulecio, P. Pendru, A. Kumari and S. Bhanja, "Magnetic Cellular
Automata Wire Architectures", IEEE Transactions on Nanotechnology,
vol.10, no.6, pp.1243-1248, 2011.

[4] R. Nakatani, H. Nomura and Y. Endo, "Magnetic Logic Devices
Composed of Permalloy Dots," Journal of Physics: Conference Series,
vol. 165, pp. 012030, IOP Publishing, 2009.

[5] J. Pulecio and S. Bhanja, "Magnetic Cellular Automata Coplanar
Cross-Wire Systems," Journal of Applied Physics, vol. 107, no. 3,
pp. 034308-034308, 2010.

[6] D. K. Karunaratne and S. Bhanja, "Study of Single Layer and
Multilayer Nano-magnetic Logic Architectures," Journal of Applied
Physics, Accepted, 2011.

[7] M. Niemier, M. Alam, X. Hu, G. Bernstein, W. Porod, M. Putney and
J. DeAngelis, "Clocking Structures and Power Analysis for Nanomagnet
based Logic Devices," International symposium on Low power electronics
and design (ACM), pp. 26-31, 2007.

[8] A. Kumari and S. Bhanja, "Landauer Clocking for Magnetic Cellular
Automata (MCA) Arrays," IEEE Transactions on VLSI, issn. 1063-8210,
2010.

[9] D. Carlton, N. Emley, E. Tuchfeld and J. Bokor, "Simulation
Studies of Nanomagnet-Based Logic Architecture," Nano Letters, vol. 8,
no. 12, pp. 4173-4178, 2008.

[10] D. Karunaratne, J. Pulecio and S. Bhanja, "Driving Magnetic Cells
for Information Storage and Propagation," IEEE Nanotechnology
Materials and Devices Conference (NMDC), pp. 360-363, 2010.

[11] J. Das, S. M. Alam and S. Bhanja, "Low Power Magnetic Quantum
Cellular Automata Realization Using Magnetic Multi-Layer Structures,"
IEEE Journal on Emerging and Selected Topics in CAS, vol. 1, no. 3,
pp. 267-276, Sept. 2011.

[12] B. Behin-Aein, D. Datta, S. Salahuddin and S. Datta, "Proposal
for an All-spin Logic Device with Built-in Memory," Nanture
Nanotechnogy, vol. 5, no. 4, pp. 266-270, 2010.

[13] C. Augustine, B. Behin-Aein, X. Fong, and K. Roy, "A design
methodology and device/circuit/architecture compatible simulation
framework for low-power magnetic quantum cellular automata systems,"
in Proceedings of the 2009 Asia and South Pacific Design Automation
Conference, pp. 847-852, IEEE Press, 2009.

[14] S. R. Patil, X. Yao, H. Meng, J-P Wang and D. J. Lilja, "Design
of a Spintronic Arithmetic and Logic Unit using Magnetic Tunnel
Junctions," Proceedings of the 5th conference on Computing frontiers,
ACM, pp. 171-178, 2008.

[15] J. Das, S. M. Alam and S. Bhanja, "Ultra-low Power Hybrid
CMOS-Magnetic Logic Architecture," (Accepted) for IEEE Transactions on
Circuits and Systems I, 2012.

[16] K. Roy, S. Bandyopadhyay and J. Atulasimha, "Hybrid spintronics
and straintronics: A magnetic technology for ultra low energy
computing and signal processing," Applied Physics Letters, vol. 99,
pp. 063108, 2011.

[17] J. Pulecio, S. Sarkar and S. Bhanja, "An Experimental
Demonstration of the Viability of Energy Minimizing Computing Using
Nano-Magnets," (Accepted) IEEE Conference on Nanotechnology, 2011.

[18] S. Sarkar and S. Bhanja, "Direct quadratic minimization using
magnetic field-based computing," IEEE International Workshop on Design
and Test of Nano Devices, Circuits and Systems, pp. 31-34, 2008.

Back to Contents

Paper Submission Deadlines

BSN'12 - Int'l Conference on Wearable and Implantable Body Sensor Networks
London, UK
May 10-12, 2012
Deadline: Jan 13, 2012 (Abstracts due: Jan 6, 2012)
http://www.bsn2012.org

HOST'12 - Int'l Symposium on Hardware-Oriented Security and Trust
San Francisco, CA (in conjunction with DAC)
June 3-4, 2012
Deadline: Jan 20, 2012
http://www.hostsymposium.org

AHS'12 - NASA/ESA Conference on Adaptive Hardware and Systems
Nuremburg, Germany
Jun 25-28, 2012
Deadline: Jan 23, 2012
http://www.see.ed.ac.uk/ahs2012/

VLSI Design Journal
(Special Issue in "New Algorithmic Techniques for EDA Problems")
Publication date: Jun 22, 2012
Deadline: Feb 3, 2012
http://www.hindawi.com/journals/vlsi/si/eda/

MEMOCODE'12 - Int'l Conference on Formal Methods and Models for Codesign
Arlington, Virginia
July 16-18, 2012
Deadline: Mar 2, 2012 (abstract)
Mar 9, 2012 (paper)
http://www.memocode-conference.com

PACT'12 - Int'l Conference on Parallel Architectures and Compilation
Techniques
Minneapolis, MN
Sep 21-25, 2012
Deadline: Mar 25, 2012
http://www.pactconf.org

ASQED'12 - Asia Symposium on Quality Electronic Design
Kuala Lumpur, Malaysia
Jul 10-12, 2012
Deadline: Apr 4, 2012
http://www.asqed.org/

VLSI-SoC'12 - Int'l Conference on Very Large Scale Integration and System on Chip
Santa Cruz, CA
Oct 7-12, 2012
Deadline: Apr 9, 2012
http://vlsisoc2012.soe.ucsc.edu/

RTCSA'12 - Int'l Conference on Embedded and Real-Time Computing Systems and Applications
Seoul, Korea
Aug 20-22, 2012
Deadline: Apr 16, 2012
http://rtcsa.konkuk.ac.kr/

Back to Contents

Upcoming Conferences and Symposia

VLSI'12 - Int'l Conference on VLSI Design
Hyderabad, India
Jan 7-11, 2012
http://vlsiconference.com/vlsi2012/

TAU'12 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
Taipei, Taiwan, R.O.C
Jan 18 - 20, 2012
http://www.tauworkshop.com/

HiPEAC'12: Int'l Conference on High Performance Embedded Architectures & Compilers
Paris, France
Jan 23-25, 2012
http://www.hipeac.net/

ASP-DAC'12 - Asia and South Pacific Design Automation Conference
Sydney, Australia
Jan 30 - Feb 2, 2012
http://www.cse.unsw.edu.au/~babaks/aspdac/

ISSCC'12 - Int'l Solid-State Circuits Conference
San Francisco, CA
Feb 19-23, 2012
http://isscc.org/

DATE'12 - Design Automation and Test in Europe
Dresden, Germany
Mar 12-16, 2012
http://www.date-conference.com/

ISQED'12 - Int'l Symposium on Quality Electronic Design
Santa Clara, CA
Mar 19-21, 2012
http://www.isqed.org/

SPL'12 - Southern Conference on Programmable Logic
Bento Gonçalves, Brazil
Mar 21-23, 2012
http://www.splconf.org/

ISPD'12 - Int'l Symposium on Physical Design
Napa, CA
Mar 25-28, 2012
http://www.ispd.cc

ASYNC'12 - Int'l Symposium on Asynchronous Circuits and Systems
(co-located with NOCS'12)
Copenhagen, Denmark
May 7-9, 2012
http://asyncsymposium.org

NOCS'12 - Int'l Symposium on Networks-on-Chip
(co-located with ASYNC'12)
Copenhagen, Denmark
May 9-11, 2012
http://www2.imm.dtu.dk/projects/nocs_2012/nocs/Home.html

ISCAS'12 - Int'l Symposium on Circuits and Systems
COEX, Seoul, Korea
May 20-23, 2012
http://iscas2012.org/

DAC'12 - Design Automation Conference
San Fransisco, CA
Jun 3-7, 2012
Deadline: Dec 5, 2011 (Abstracts due: Nov 29, 2011)
http://www2.dac.com/

ISCA'11 - Int'l Symposium Computer Architecture
Portland, OR
Jun 9-13, 2012
http://isca2012.ittc.ku.edu/

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Upcoming Funding Opportunities

ASEE

Office of Naval Research (ONR) Sabbatical Leave Program
Deadline: N/A
http://onr.asee.org/

Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Deadline: Continuous
http://www.asee.org/fellowships/nrl/about.cfm

DARPA

Microsystems Technology Office-Wide Broad Agency - DARPA-BAA-10-35
Deadline: September 1, 2012
https://www.fbo.gov/spg/ODA/DARPA/CMO/DARPA-BAA-10-35/listing.html

DOD

Robust Computational Intelligence - AFOSR-BAA-2011-01
Deadline: Continuous
http://www.grants.gov/search/search.do?oppId=88213&mode=VIEW

Systems and Software - AFOSR-BAA-2011-01
Deadline: Continuous
http://www.grants.gov/search/search.do?oppId=88213&mode=VIEW

ERDC BAA - Computational Science and Engineering (ITL-1)
Deadline: Continuous
http://www.mvk.usace.army.mil/contract/docs/BAA.pdf

Advanced Distributed Sensor Technologies - BAA 57-09-06
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm

Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm

High Performance Computing on Massively Parallel Architectures (BAA 64-09-01)
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm

ASEE-NRL Postdoctoral Fellowship Program
Deadline: N/A
http://hroffice.nrl.navy.mil/jobs/postdoc.htm

DOE

Postdoctoral Appointments
Deadline: N/A
http://www.sandia.gov/careers/postdoc.html

Sabbaticals and Faculty Appointments
Deadline: continuous
http://www.nrel.gov/rpp/sabbaticals.html

McDonnell Foundation

Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Deadline: continuous
http://www.jsmf.org/programs/cs/

NSF

National Robotics Initiative (NRI)
Letter of Intent: December 15, 2011
Full Proposal Deadline: January 18, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf11553

Industry/University Cooperative Research Centers Program (I/UCRC)
Letter of Intent Deadline Date: January 2, 2012
Full Proposal Deadline Date: March 6, 2012
http://www.nsf.gov/publications/pub_summ.jsp?WT.z_pims_id=5501&ods_key=nsf12516

Major Research Instrumentation Program
Full Proposal Deadline Date: January 26, 2012
http://www.nsf.gov/publications/pub_summ.jsp?WT.z_pims_id=5260&ods_key=nsf11503

SRC

Integrated Circuit and Systems Sciences (ICSS) - Integrated System Design
White Paper Deadline Date: January 25, 2012
http://www.src.org/compete/s201121/

Integrated Circuit and Systems Sciences (ICSS) - Circuit Design
White Paper Deadline Date: January 25, 2012
http://www.src.org/compete/s201116/

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Call for Papers: VLSI Design Journal Special Issue on New Algorithmic Techniques for EDA Problems

CALL FOR PAPERS
VLSI Design Journal Call for Papers (deadline Feb. 3, 2012):
Special Issue on New Algorithmic Techniques for EDA Problems

Please see http://www.hindawi.com/journals/vlsi/si/eda/ for details.
The details are also given below.

Original papers are invited for a special issue of the VLSI Design
journal on "New Algorithmic Techniques in EDA". There are two broad
sets of effects that result from the rapidly decreasing feature sizes
in CMOS VLSI (ASICs, SoCs and microprocessor designs). (a) Significant
increase in the number and the diversity of systems that are
implemented on a single chip (b) Further exacerbation of old problems
and the introduction of new ones such as electrical/physical effects
like power dissipation and leakage/temperature issues at all levels,
lithography and manufacturing problems leading to appreciable
variability, and reliability of the design stemming from reduced
feature sizes, to name a few. These issues present significant
challenges to the entire range of EDA tools from ESL (e.g., memory
synthesis and hierarchy design, effective power analysis and
optimization) to gate-level synthesis (e.g., detailed power
optimization across millions of gates under timing yield and
voltage-island constraints). EDA software has thus become immensely
complex, and algorithmic innovations are needed to tackle these new
problems with efficiency and efficacy at various stages of the VLSI
design flow (e.g., ESL including high-level synthesis, logic/physical
synthesis, physical extraction and timing models,
variability/manufacturing aware optimization, simulation and analysis,
and verification).

TOPICS

We are thus asking for original paper submissions addressing critical
problems in EDA using effective algorithmic techniques that are either
new or uncommon in EDA. More formally put, the desired algorithmic
techniques are those that either (a) are completely new in their usage
in the EDA domain, or (b) have been proposed only over the last five
years or so or (c) have been proposed more than five years back, but
have been used sparsely in EDA. Potential algorithmic approaches
include, but are not limited to:

** Various polynomial time approximation schemes (e.g., PTAS, EPTAS, FPTAS)
** Randomized algorithms
** Discretized network flow (DNF)
** Multilevel techniques for scalability
** Parallel processing (especially for multicore CPU/GPU processors)
including concurrent data structures
** Metaheuristics, for example, tabu search, greedy randomized adaptive
search procedures (grasp), ant colony optimization, multistart methods,
and constraint satisfaction
** Machine learning and statistical techniques
** Data mining techniques

The proposed algorithms should empirically demonstrate efficacy in
solving the targeted EDA problems. When submitting your paper to this
special issue, please include a new section titled "New Algorithmic
Technique(s) Used" that immediately follows the "Introduction"
section, for an explicit identification of the algorithmic
technique(s) used, and a justification, possibly with citations, that
they fit into one of the above categories (a-c). Also, as with any
other journal publication, if the submission is an extension to a
conference paper, please also include a paragraph of justification in
the "Introduction" section (at least 30% new material is required).

SUBMISSIONS

Before submission authors should carefully read over the journal's Author
Guidelines, which are located at

http://www.hindawi.com/journals/vlsi/guidelines/

Prospective authors should submit an electronic copy of their complete
manuscript through the journal Manuscript Tracking System at

http://mts.hindawi.com/

according to the following timetable:

IMPORTANT DATES

Manuscript Due Friday, 3 February 2012
First Round of Reviews Friday, 27 April 2012
Publication Date Friday, 22 June 2012

FURTHER INFORMATION

Lead Guest Editor:
Shantanu Dutt, dutt@uic.edu, Department of ECE,
University of Illinois at Chicago, Chicago, IL, USA
Guest Editors:
Dinesh Mehta, dmehta@mines.edu, Department of EECS,
Colorado School of Mines, Golden, Co, USA
Gi-Joon Nam, gnam@us.ibm.com, IBM Research Labs, Austin, TX, USA

Back to Contents

Call for Papers: International Symposium on Hardware-Oriented Security and Trust (HOST)

HOST-2012
IEEE International Symposium on HARDWARE-ORIENTED SECURITY and TRUST
June 3-4, Moscone Center, San Francisco, CA
Held in conjunction with DAC-2012 (http://www.hostsymposium.org)

Call for Papers

A wide range of applications, from secure RFID tagging to high-end
trusted computing, relies on dedicated and trusted hardware
platforms. The security and trustworthiness of such hardware designs
are critical to their successful deployment and operation. Recent
advances in tampering and reverse engineering show that important
challenges lie ahead. For example, secure electronic designs may be
affected by malicious circuits, Trojans that alter system
operation. Furthermore, dedicated secure hardware implementations are
susceptible to novel forms of attack that exploit side-channel leakage
and faults. Third, the globalized, horizontal semiconductor business
model raises concerns of trust and intellectual-property
protection. HOST 2012 is a forum for novel solutions to address these
challenges. Innovative test mechanisms may reveal Trojans in a design
before they are able to do harm. Implementation attacks may be
thwarted using side-channel resistant design or fault-tolerant
designs. New security-aware design tools can assist a designer in
implementing critical and trusted functionality, quickly and
efficiently.

The IEEE International Symposium on Hardware Oriented Security and
Trust seeks original contributions in the area of hardware-oriented
security. This includes tools, design methods, architectures, and
circuits. In addition, novel applications of secure hardware are
especially welcome. HOST 2012 seeks contributions based on, but not
limited to, the following topics.

* Trojan detection and isolation
* Implementation attacks and countermeasures
* Side channel analysis and fault analysis
* Intellectual property protection and metering
* Tools and methodologies for secure hardware design
* Hardware architectures for cryptography
* Hardware security primitives: PUFs and TRNGs
* Applications of secure hardware
* Interaction of secure hardware and software

To present at the symposium, submit an Acrobat (PDF) version of your
paper on the symposium submission website. The page limit is 6 pages,
double column, IEEE format, with a minimum font size of 10
points. Submissions must be anonymous and must not identify the
submitting authors, directly or indirectly, anywhere in the
manuscript.

SCHEDULE:

Submission of Paper: January 20, 2012
Notification of Acceptance: March 23, 2012
Camera Ready Paper: April 13, 2012

Back to Contents

Call for Papers: TCAD Special Section on Three-dimensional Integrated Circuits and Microarchitectures

CALL FOR PAPERS: IEEE Transactions on CAD
Special Section on Three-dimensional Integrated Circuits and Microarchitectures

In recent years, the area of three-dimensional (3D) Integrated
Circuits has become a very attractive research topic due to its
potential for extending MooreÕs momentum in the next decade. The key
benefits of 3D ICs over traditional two-dimensional chips include the
potential of reduced overheads for global interconnects, higher
packing densities and smaller footprints, heterogeneous integration,
and faster times-to-market. To efficiently exploit the benefits of 3D
technologies, design techniques and methodologies for supporting 3D
designs are imperative; design space exploration at the architectural
level is also essential to fully take advantage of the 3D integration
technologies to build a high- performance, energy-efficient integrated
systems, GPUs, system-on-chips, heterogeneous systems, and other
integrated systems.

We are pleased to announce a call for papers for a special section of
TCAD on Three-dimensional (3D) Integrated Circuits. We welcome
submissions to this special section based on new, unpublished
contributions. Submissions may also be based on work previously
published in refereed conferences/workshops; if so, the submission
must contain at least 30% new materials, and the authors must provide
a cover letter clearly stating how the submission differs from and/or
expands on the previously-published work.

Areas of interest for this special section include (but are not limited to) the
following topics:

* Physical design methodologies/tools/algorithms for 3D
* High-level synthesis/logic synthesis for 3D ICs
* ESL design methodologies and tools for 3D ICs
* Thermal analysis and thermal-aware designs
* 3D architectures and design space exploration
* 3D Test, design-for-test, and debug techniques
* Signal and power integrity, and ESD in 3D
* Chip-package co-design for 3D
* Economic benefit/cost trade-off studies
* Application, product, or test-chip case studies

Please submit your paper at the TCAD website,

http://mc.manuscriptcentral.com/tcad

Please specify "Special Section on 3D ICs and Microarchitectures" on
your cover page and in the notes section of the Web site submission
form.

IMPORTANT DATES

Submission Deadline: 15 March 2012
Acceptance Notice: 1 July 2012
Final Manuscript Due: 1 August 2012

GUEST EDITORS

Yuan Xie, Pennsylvania State University, yuanxie@cse.psu.edu
Gabriel H. Loh, AMD Research. Gabe.loh@amd.com

Back to Contents

Call for Papers: International Conference on Formal Methods and Models for Codesign (MEMOCODE)

ACM/IEEE Tenth International Conference on Formal Methods and Models for Codesign

MEMOCODE 2012

http://www.memocode-conference.com

Arlington, Virginia
July 16-18, 2012

The goal of MEMOCODE 2012, the tenth in a series of successful
international conferences, is to gather researchers and practitioners
in the field of the design of modern hardware and software system to
explore ways in which future design methods can benefit from new
results on formal methods.

IMPORTANT DATES

Abstract submission deadline: March 2, 2012
Paper submission deadline: March 9, 2012
Notification of acceptance: May 4, 2012
Final Version for Papers: May 18, 2012

Hardware-software systems face increasing design complexity including
tighter constraints on timing, power, costs, and reliability. MEMOCODE
seeks submissions that present novel formal methods and design
techniques addressing these issues to create, refine, and verify
hardware/software systems. We also invite application-oriented papers,
and especially encourage submissions that highlight the design
perspective of formal methods and models, including success stories
and demonstrations of hardware/software codesign. Furthermore, we
invite poster presentations describing ongoing work with promising
preliminary results.

Topics of interest for regular submissions include but are not limited
to

* system- and transaction-level modeling and verification, abstraction
and refinement between different modeling levels, formal,
semi-formal, and specification-driven verification,

* design and verification methods for composition of concurrent
systems: multi-core platform architectures, systems-on-chip,
networks-on-chip,

* formal methods and tools for hardware and software verification
including theorem proving, decision procedures,

* non-traditional and domain-specific design languages for hardware
and software, novel models of computation, and new design paradigms
that unify hardware and software design,

* system-level estimation of performance and power in heterogeneous
hardware/software architectures,

* applications and demonstrators of formal design methodologies and
case studies of innovative system-level design flows,

* modeling and reuse of intellectual property at system-level, and

* design abstraction and high-level design demonstrating productivity
and quality in generating and validating RTL and software.

PROCEEDINGS

Conference proceedings will be published by the IEEE Computer Society.

SUBMISSION

Submissions of research and experience papers will only be accepted
through the conference website. Papers must not exceed 10 pages and
must be formatted following IEEE Computer Society guidelines.
Submissions must be written in English, describe original work, and
not substantially overlap papers that have been published or are being
submitted to a journal or another conference with published
proceedings. Poster submissions should consist of an abstract of at
most 250 words. The abstract will be distributed to the conference
attendants but will not be published. Note that the poster deadline is
different from the paper deadline.

SUBMISSION WEBSITE

http://www.easychair.org/conferences/?conf=memocode2012

DESIGN COMPETITION

MEMOCODE will again have a design contest. The contest will start
March 1, 2012. The deadline for submission is 31 March 2012 and the
notification of the results is on May 13, 2012. The conference will
sponsor at least two prize categories, each with a significant cash
award. In past editions we awarded a $1000 prize in each of the two
categories. Each team that submits a complete and working entry will
be invited to submit for review a 2-page abstract for the formal
conference proceedings and present a poster at the conference; winning
teams will be invited to contribute a 4-page short paper and present
their work at the conference. Each team submitting a completed and
working entry will also receive a commemorative plaque with their name
and results. Please refer to the website for more information and
updates.

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SIGDA E-News 1 January 2012, Vol. 42, No. 1