SIGDA E-News 1 March 2012, Vol. 42, No. 03

1 March 2012, Vol. 42, No. 3
Online archive: http://www.sigda.org/newsletter

SIGDA News
From: Lin Yuan <yuanl@synopsys.com>
What is Systems Biology?
Contributing authors: Smita Krishnaswamy <sk3349@columbia.edu>
From: Srinivas Katkoori <katkoori@cse.usf.edu>
Paper Submission Deadlines
From: Debjit Sinha <debjitsinha@yahoo.com>
Upcoming Conferences and Symposia
From: Debjit Sinha <debjitsinha@yahoo.com>
Upcoming Funding Opportunities
From: Sudeep Pasricha <sudeep@colostate.edu>
Call for Papers: New Algorithmic Techniques for EDA Problems (deadline extended to March 30)
From: Shantanu Dutt <dutt@ece.uic.edu>
Call for Papers: TCAD Special Section on Three-dimensional Integrated Circuits and Microarchitectures
From: Deming Chen <dchen@illinois.edu>
Call for Papers: International Conference on Formal Methods and Models for Codesign (MEMOCODE)
From: Luca Carloni <luca@cs.columbia.edu>
Call for Papers: International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
From: Sudeep Pasricha <sudeep@colostate.edu>
Call for Papers: International Symposium on Low Power Electronics and Design (ISLPED)
From: Pai Chou <phchou@uci.edu>
Call for Papers: JETC Special Issue on Reliability and Device Degradation in Emerging Technologies
From: Fadi H Gebara <fhgebara@us.ibm.com>
Call for Papers: International Workshop on Logic & Synthesis (IWLS)
From: Stephen A. Edwards <sedwards@cs.columbia.edu>
Call for Participation: International Symposium on Physical Design (ISPD)
From: Azadeh Davoodi <adavoodi@wisc.edu>
Call for Participation: Ph.D. Forum at DAC
From: Laleh Behjat <laleh@ucalgary.ca>
Call for Papers: International Conference on Very Large Scale Integration (VLSI-SOC)
From: Matthew Guthaus <mrg@ucsc.edu>
Call for Papers: ACM Student Research Competition (SRC) at Design Automation Conference
From: Srinivas Katkoori <katkoori@cse.usf.edu>
Call for Papers: IEEE Annual Symposium on VLSI Design (ISVLSI)
From: Ankur Srivastava <ankurs@umd.edu>
Call for Papers: Special Issue on Practical Parallel EDA
From: Rasit O. Topaloglu <rasit@us.ibm.com>
Call for Papers: Foundations and Trends in Electronic Design Automation (FnTEDA)
From: Tanya Capawana <tanya.capawana@nowpublishers.com>
Call for Papers: International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
From: Naehyuck Chang <naehyuck@elpl.snu.ac.kr>
Call for Papers: Embedded Systems Week
From: Luca Carloni <luca@cs.columbia.edu>
Call for Abstracts: International Workshop on Bio-Design Automation (IWBDA)
From: Natasa Miskov-Zivanov <nam66@pitt.edu>
Call for Tutorials: Midwest Symposium on Circuits and Systems (MWSCAS)
From: Ruben Alejos Palomares <ruben.alejos@udlap.mx>

Comments from the Editors

Dear ACM/SIGDA members,

In accordance with ACM Bylaw 6, the following SIGs will hold elections
in 2012: SIGACCESS, SIGACT, SIGCHI, SIGDA, ACM SIGGRAPH, SIGITE,
SIGPLAN, SIGSIM and SIGSOFT.

ACM Policy and Procedures require that those SIGs holding elections
notify their membership of candidates for elected offices. To see the
slate of candidates, please visit the 2012 ACM SIG Election site,
http://www.acm.org/sigs/elections.

In accordance with the SIG Bylaws, additional candidates may be placed
on the ballot by petition. All candidates must be Professional Members
of ACM, as well as members of the SIG. Anyone interested in
petitioning must inform ACM Headquarters (Pat Ryan, ACM, 2 Penn Plaza,
Suite 701, NY, NY 10121; ryan_p@acm.org) and the SIG Viability Advisor
(Barbara Boucher Owens, owensb@acm.org) of their intent to petition by
March 15.

Additional information will appear in the February or March issue of
ACM MemberNet and on the 2012 ACM SIG Election site.

Matthew Guthaus, E-Newsletter Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Sudeep Pasricha, E-Newsletter Associate Editor;
Srinivas Katkoori, E-Newsletter Associate Editor

Back to Contents

SIGDA News

"Synopsys Completes Acquisition of Magma Design Automation"
http://www10.edacafe.com/nbc/articles/1/1062642/Synopsys-Completes-Acquisition-M...
Synopsys, Inc. has completed its acquisition of Magma Design
Automation Inc. a provider of chip design software headquartered in
San Jose, California. The combination of Synopsys and Magma will
enable the company to more rapidly meet the needs of leading-edge
semiconductor designers for ever more sophisticated design tools.

"49th DAC Announces the 2012 A. Richard Newton Graduate Scholarship
to Support Research in EDA"
http://www10.edacafe.com/nbc/articles/1/1062569/49th-Design-Automation-Conferenc...
The Design Automation Conference (DAC), the premier event on
automation and design of electronic systems, annually awards a
scholarship in memory of Dr A. Richard Newton to support graduate
research and study in electronic design automation (EDA). The $24K
scholarship supports graduate students or young faculty investigators
embarking on new research in the field of EDA. Applications must be
submitted electronically by March 18th, 2012. Full details are on the
DAC website at www.dac.com

"Mentor Graphics Drives Broader Adoption of UVM"
http://www10.edacafe.com/nbc/articles/1/1062370/Mentor-Graphics-Drives-Broader-A...
Mentor Graphics Corporation today announced expanded support for the
Universal Verification Methodology (UVM). The UVM delivers
productivity gains made possible by reuse in functional
verification. For verification teams with minimal exposure to UVM, the
first step to implement a UVM-based verification environment is simply
getting started. To facilitate that first step, Mentor introduces UVM
Express, a way to progressively adopt a UVM methodology. Other
verification teams have an established UVM-based verification
environment, but are challenged to move their trusted verification
approach up in abstraction where a new level of system verification
can be achieved. For those verification teams, Mentor introduces UVM
Connect, which provides standard TLM 1.0 and TLM 2.0 connectivity
between models written in SystemC and UVM SystemVerilog.

"Accellera Systems Initiative Announces IEEE 1666(TM) SystemC(TM) Language
Standard for ESL esign Is Available for Download at No Charge"
http://www10.edacafe.com/nbc/articles/1/1062135/Accellera-Systems-Initiative-Ann...
The Accellera Systems Initiative announced today that the IEEE
Standards Association (IEEE-SA), a globally recognized
standards-setting body within the IEEE, now offers the latest version
of the IEEE 1666™ "Standard SystemC Language Reference Manual," for
download at no charge, as part of the IEEE Get program.

"27 of 33 IC Product Categories Will See Market Growth in 2012 says IC Insights"
http://www10.edacafe.com/nbc/articles/1/1057457/27-33-IC-Product-Categories-Will...
IC Insights forecasts that 27 of the 33 major IC product categories
defined by WSTS will experience growth in 2012, with 11 segments
expected to grow better than the 7% forecast for the total IC
industry. Six categories are forecast to show double-digit growth.
The numbers stand in sharp contrast to the 15 products that showed
positive growth and 18 that experienced a decline in 2011.

"Toshiba starts mass production of 19nm NAND flash"
http://www10.edacafe.com/goto.php?eurl=aHR0cDovL3d3dy5kaWdpdGltZXMuY29tL3ByaW50L...
Toshiba has developed a 3-bit-per-cell 128Gb chip, which entered mass
production using the company's 19nm process technology earlier in
February 2012, according to the NAND flash vendor. Toshiba said that
the new 3-bit-per-cell 19nm generation device uses a three-step
programming algorithm and air-gap technology for transistors,
effectively reducing coupling between memory cells down to 5% and
achieving a write speed performance of 18MB/s.

"Columbia University and Semiconductor Research Corporation Breathe New Life into Scalability by Integrating Voltage Regulators Directly onto ICs"
http://www10.edacafe.com/nbc/articles/1/1062392/Columbia-University-Semiconducto...
Semiconductor Research Corporation (SRC), the world's leading
university-research consortium for semiconductors and related
technologies, and Columbia University today announced research results
that place industry focus back onto voltage regulators as a solution
for continued processor scalability. Having just proven a new
generation of integrated voltage regulator (IVR) that features energy
densities more than ten times that of present state-of-art inductors
available on computer chips, the team is preparing to test a second
round of prototypes.

"IBM reports breakthroughs in quantum computing quest"
http://www.eetimes.com/electronics-news/4237101/IBM-reports-progress-on-quantum-...
The last major engineering hurdle to quantum computers—millisecond
coherence times—has been surmounted by researchers at IBM Research,
making commercialization of the technology possible "within our
lifetimes," according to Matthias Steffen, manager of IBM's
Experimental Quantum Computing group.

"ISSCC highlights sensors and semiconductor technology in medicine"
http://www.eetimes.com/electronics-news/4236898/ISSC-highlights-sensors-and-semi...
Session 17 at this year's International Solid-State Circuits
Conference (ISSCC) focused on the diagnostic and therapeutic
technologies for health, leveraging the recent advances in sensor and
semiconductor technologies.

"Magma's Madhavan won't join Synopsys"
http://www.eetimes.com/electronics-news/4236798/Magma-s-Madhavan-won-t-join-Syno...
EDA and IP vendor Synopsys Inc. said Wednesday (Feb. 22) it closed the
$523 million acquisition of long-time rival Magma Design Automation
Inc. and revealed that Rajeev Madhavan, Magma's chairman and CEO,
would not be joining Synopsys as a result.

"Micron launches lower power DDR3 DRAM"
http://www.eetimes.com/electronics-news/4236139/Micron-launches-lower-power-DDR3...
Memory chipmaker Micron Technology Inc. (Boise, Idaho) has launched a
lower power version of the DDR3 type of DRAM under the label DDR3Lm
with 2- and 4-Gbit capacity memories.

Back to Contents

What is Systems Biology?

Smita Krishnaswamy, Columbia University
sk3349@columbia.edu

Systems biology [1,2] is an exciting and emerging field concerned elucidating
biological systems by analyzing interactions between components and the
resulting behavior. The end goal of systems biology research is to understand
biological systems enough to predict and even control their behavior
(especially in cases of faulty behaviors, like cancer). Much like electronic
systems, biological systems have a vast number of interacting components
including:

1) DNA: the human genome consists of about 3 billion base pairs that
code for 23,000 genes and an unknown number of regulatory sequences,
non-coding RNA sequences, introns, and regions of unknown functionality
that was once dismissed as “junk DNA.”

2) RNA: at any point in time the cell contains transcripts of genetic
information for protein synthesis, as well as regulatory sections of RNA
that are designed to modify or silence other RNA messages.

3) Proteins: each cell consists of thousands of proteins that are essentially
devices that do the work of the cell. Many proteins also have computationally
interesting functions such as communicating and integrating inputs from
the outside environment (in a process known as signal transduction) or
regulating the expression of another gene. Other proteins have structural
functions such as filament building or secretion of the extracellular matrix
that maintains tissue integrity.

The above components interact with each other in complex ways. For example,
gene expression is tightly controlled by transcription-factor proteins that
bind to a regulatory region of the DNA to increase or decrease transcription.
Transcription factors can be in turn controlled by upstream events such as
external messages (chemicals, other cells, pressure, heat, light signals),
and internal events such as levels of glucose, cell cycle clocks, and finally,
other proteins which are the products of other genes. Therefore there are
large and complex systems with logic and feedback in biology.

The advent of high-throughput technologies for genomics, transcriptomics,
and proteomics makes studying these components and their joint effects possible,
to some degree, for the first time. Next generation sequencing technologies
make rapid and parallel genome sequencing possible, RNAseq or RNA sequencing
technologies reveal which genes are actually being expressed in a cell as
proteins, and new proteomic techniques such as flow and mass cytometry make it
possible to measure the activity of proteins within the cell. The large amount
of data that such technologies generate about biological systems need to be
integrated into descriptive and predictive mathematical models. Therefore
studying such a system becomes an interdisciplinary effort in which biologists,
computer scientists, statisticians, physicists, and engineers collaborate and
tackle different aspects of the problem.

EDA experts generally have an advantage in tackling problems in systems biology
due to their experience in dealing with other types of large and complex systems.
However, there are many differences between electronic and biological systems.
Biological systems are more complex, inherently probabilistic, and less respectful
of abstraction and modularity. Several examples of such “messyness” are given below:

1) Signals can be encoded in various ways within the same system or network.
For instance, some signals are encoded by the abundance of a particular type
of molecule. Such signals have to diffuse through the cytoplasm and are subject
to the statistical mechanics of that process. However, other signals are
transmitted by cascades of protein activations. These are largely binary events
with regular timing.

2) There are more breaches of barriers between levels of abstraction. In a computer,
for instance, the CPU is neatly separated from the memory, as are combinational
logic gates from state-holding elements. In biology, however, even pieces of a
cell membrane (such as inositol triphosphate) can break off and carry a signal.

3) There are no design specs. The design and functionality of a system has to
be reverse-engineered or “learned” (often using statistical and machine learning
techniques) from highly noisy and limited observations. Electronic systems on the
other hand can be tested rather easily given inputs that exercise the system,
and further they can be designed for testability.

Scientists have modeled aspects of biological systems as interaction networks,
graphs, probabilistic graphical models (such as Bayesian networks [3]), control
systems, and even as logic circuits [5]. However, all of these models have limitations
in terms of computational complexity and accuracy.

In summary, the state of science and technology is advancing to the point where
we can begin to coherently think of life as consisting of biological systems that
can be modeled, controlled and perhaps even rebuilt. This effort to understand
biological systems is not limited to classically trained biologists alone, but
calls for the collaborative expertise [6,7] of computer scientists, engineers,
physicists [4], and mathematicians.

References:

[1] U. Alon, An Introduction to Systems Biology: Design Principles
of Biological Circuits. Chapman & Hall. 2006.

[2] K. Kaneko, Life: An Introduction to Complex Systems Biology.
Springer-Verlag, 2006.

[3] D. Pe'er, et al., “Bayesian Network Analysis of Signaling
Networks: A Primer,” Science Stke, 2005, 281, pp. 14.

[4] R. M. J. Cotterill, Biophysics : An Introduction. Wiley. 2002.

[5] J. Saez-Rodriguez, et al., “Discrete Logic Modeling as a means
to link Protein Signaling Networks with Functional Analysis of Mammalian
Signal Transduction,” Molecular and Systems Biology, 2009, vol. 5, p. 331.

[6] Wholecell Project, Stanford University, http://wholecell.stanford.edu/.

[7] Encode Project, http://www.genome.gov/10005107.

Back to Contents

Paper Submission Deadlines

SLIP'12 - System Level Interconnect Prediction
(co-located with DAC'12)
San Francisco, CA
June 3, 2012
Deadline: Mar 5, 2012 (Abstracts due: Feb 27, 2012)
http://www.sliponline.org

ISLPED'12 - Int'l Symposium on Low Power Electronics and Design
Redondo Beach, CA USA
July 30-Aug 1, 2012
Deadline: Mar 9, 2012 (Abstracts due: Mar 2, 2012)
http://www.islped.org

ISVLSI'12 - IEEE Annual Symposium on VLSI Design
Amherst, USA
Aug 19-21, 2012
Deadline: Mar 9, 2012
http://www.eng.ucy.ac.cy/theocharides/isvlsi12/index.htm

IWLS'12 - Int'l Workshop on Logic & Synthesis
University of California, Berkeley
June 1-3, 2012
Deadline: Mar 16, 2012 (Abstracts due: Mar 9, 2012)
http://www.iwls.org

MEMOCODE'12 - Int'l Conference on Formal Methods and Models for Codesign
Arlington, VA
Jul 16-18, 2012
Deadline: Mar 16, 2012 (Abstracts due: Mar 9, 2012)
http://www.memocode-conference.com

PACT'12 - Int'l Conference on Parallel Architectures and Compilation
Techniques
Minneapolis, MN
Sep 21-25, 2012
Deadline: Mar 25, 2012
http://www.pactconf.org

BodyNets'12 - Int'l Conference on Body Area Networks
Oslo, Norway
Sep 24-26, 2012
Deadline: Apr 1, 2012
http://www.bodynets.org

IWBDA'12 - Int'l Workshop on Bio-Design Automation
San Francisco, CA (Co-located with DAC'12)
Jun 4-5, 2012
Deadline: Apr 2, 2012
http://iwbda2012.csb.pitt.edu

ASQED'12 - Asia Symposium on Quality Electronic Design
Kuala Lumpur, Malaysia
Jul 10-12, 2012
Deadline: Apr 4, 2012
http://www.asqed.org/

CODES+ISSS'12 - Int'l Conference on Hardware/Software Codesign and System Synthesis
Tampere, Finland
Oct 7-12, 2012
Deadline: Apr 04, 2012 (Abstracts due: Mar 28, 2012)
http://codes-isss.org/

ESWeek'12 - Embedded Systems Week
Tampere, Finland
October, 7-10, 2012
Deadline: Apr 4, 2012 (Abstracts due: Mar 28, 2012)
http://www.esweek.org/

VLSI-SOC'12 - Int'l Conference on Very Large Scale Integration and System on Chip
Santa Cruz, CA
Oct 7-12, 2012
Deadline: Apr 9, 2012
http://vlsisoc2012.soe.ucsc.edu/

DFM&Y'12 - Int'l Workshop on Design for Manufacturability & Yield
San Francisco, CA (Co-located with DAC'12)
Jun 4, 2012
Deadline: Apr 2012 (tentative)
http://vlsicad.ucsd.edu/DFMY

ICCAD'12 - Int'l Conference on Computer-Aided Design
San Jose, CA (tentative)
Nov 2011 (exact dates to be announced)
Deadline: Apr 16, 2012
http://www.iccad.com

Wireless Health'12
San Diego, CA
Oct 22-25, 2012
Deadline: Apr 20, 2012
http://www.wirelesshealth2012.org/

Back to Contents

Upcoming Conferences and Symposia

DATE'12 - Design Automation and Test in Europe
Dresden, Germany
Mar 12-16, 2012
http://www.date-conference.com/

ISQED'12 - Int'l Symposium on Quality Electronic Design
Santa Clara, CA
Mar 19-21, 2012
http://www.isqed.org/

SPL'12 - Southern Conference on Programmable Logic
Bento Gonçalves, Brazil
Mar 21-23, 2012
http://www.splconf.org/

ISPD'12 - Int'l Symposium on Physical Design
Napa, CA
Mar 25-28, 2012
http://www.ispd.cc

ASYNC'12 - Int'l Symposium on Asynchronous Circuits and Systems
(co-located with NOCS'12)
Copenhagen, Denmark
May 7-9, 2012
http://asyncsymposium.org

NOCS'12 - Int'l Symposium on Networks-on-Chip
(co-located with ASYNC'12)
Copenhagen, Denmark
May 9-11, 2012
http://www2.imm.dtu.dk/projects/nocs_2012/nocs/Home.html

EWME'12 - European Workshop on Microelectronics Education
Grenoble, France
May 9-11, 2012
http://cmp.imag.fr/conferences/ewme2012

BSN'12 - Int'l Conference on Wearable and Implantable Body Sensor Networks
London, UK
May 10-12, 2012
http://www.bsn2012.org

ISCAS'12 - Int'l Symposium on Circuits and Systems
COEX, Seoul, Korea
May 20-23, 2012
http://iscas2012.org/

DAC'12 - Design Automation Conference
San Fransisco, CA
Jun 3-7, 2012
http://www2.dac.com/

ISCA'11 - Int'l Symposium Computer Architecture
Portland, OR
Jun 9-13, 2012
http://isca2012.ittc.ku.edu/

AHS'12 - NASA/ESA Conference on Adaptive Hardware and Systems
Nuremburg, Germany
Jun 25-28, 2012
http://www.see.ed.ac.uk/ahs2012/

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Upcoming Funding Opportunities

ASEE

Office of Naval Research (ONR) Sabbatical Leave Program
Deadline: N/A
http://onr.asee.org/

Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Deadline: Continuous
http://www.asee.org/fellowships/nrl/about.cfm

DARPA

Microsystems Technology Office-Wide Broad Agency - DARPA-BAA-10-35
Deadline: September 1, 2012
https://www.fbo.gov/spg/ODA/DARPA/CMO/DARPA-BAA-10-35/listing.html

DARPA-BAA-12-24: Power Efficiency Revolution For Embedded Computing Technologies
Deadline: April 16, 2012
https://www.fbo.gov/spg/ODA/DARPA/CMO/DARPA-BAA-12-24/listing.html

DOD

Robust Computational Intelligence - AFOSR-BAA-2011-01
Deadline: Continuous
http://www.grants.gov/search/search.do?oppId=88213&mode=VIEW

Systems and Software - AFOSR-BAA-2011-01
Deadline: Continuous
http://www.grants.gov/search/search.do?oppId=88213&mode=VIEW

ERDC BAA - Computational Science and Engineering (ITL-1)
Deadline: Continuous
http://www.mvk.usace.army.mil/contract/docs/BAA.pdf

Advanced Distributed Sensor Technologies - BAA 57-09-06
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm

Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm

High Performance Computing on Massively Parallel Architectures (BAA 64-09-01)
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm

ASEE-NRL Postdoctoral Fellowship Program
Deadline: N/A
http://hroffice.nrl.navy.mil/jobs/postdoc.htm

DOE

Postdoctoral Appointments
Deadline: N/A
http://www.sandia.gov/careers/postdoc.html

Sabbaticals and Faculty Appointments
Deadline: continuous
http://www.nrel.gov/rpp/sabbaticals.html

McDonnell Foundation

Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Deadline: continuous
http://www.jsmf.org/programs/cs/

NSF

Industry/University Cooperative Research Centers Program (I/UCRC)
Deadline: March 6, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf12516

Expeditions in Computing
Deadline: March 10, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf10564

Cyber-Physical Systems (CPS)
Deadline: March 15, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf12520

Innovation Corps Program (I-Corps)
Deadline: March 15, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf11560

Cyberlearning: Transforming Education (Cyberlearning)
Deadline: March 16, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf11587

Sustainability Research Networks Competition (SRN)
Deadline: April 1, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf11574

Computing Education for the 21st Century (CE21)
Deadline: April 9, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf12527

Back to Contents

Call for Papers: New Algorithmic Techniques for EDA Problems (deadline extended to March 30)

CALL FOR PAPERS (Deadline Extended to March 30)
VLSI Design Journal Call for Papers:
Special Issue on New Algorithmic Techniques for EDA Problems

Please see http://www.hindawi.com/journals/vlsi/si/eda/ for details.
The details are also given below.

Original papers are invited for a special issue of the VLSI Design
journal on "New Algorithmic Techniques in EDA". There are two broad
sets of effects that result from the rapidly decreasing feature sizes
in CMOS VLSI (ASICs, SoCs and microprocessor designs). (a) Significant
increase in the number and the diversity of systems that are
implemented on a single chip (b) Further exacerbation of old problems
and the introduction of new ones such as electrical/physical effects
like power dissipation and leakage/temperature issues at all levels,
lithography and manufacturing problems leading to appreciable
variability, and reliability of the design stemming from reduced
feature sizes, to name a few. These issues present significant
challenges to the entire range of EDA tools from ESL (e.g., memory
synthesis and hierarchy design, effective power analysis and
optimization) to gate-level synthesis (e.g., detailed power
optimization across millions of gates under timing yield and
voltage-island constraints). EDA software has thus become immensely
complex, and algorithmic innovations are needed to tackle these new
problems with efficiency and efficacy at various stages of the VLSI
design flow (e.g., ESL including high-level synthesis, logic/physical
synthesis, physical extraction and timing models,
variability/manufacturing aware optimization, simulation and analysis,
and verification).

TOPICS

We are thus asking for original paper submissions addressing critical
problems in EDA using effective algorithmic techniques that are either
new or uncommon in EDA. More formally put, the desired algorithmic
techniques are those that either (a) are completely new in their usage
in the EDA domain, or (b) have been proposed only over the last five
years or so or (c) have been proposed more than five years back, but
have been used sparsely in EDA. Potential algorithmic approaches
include, but are not limited to:

** Various polynomial time approximation schemes (e.g., PTAS, EPTAS, FPTAS)
** Randomized algorithms
** Discretized network flow (DNF)
** Multilevel techniques for scalability
** Parallel processing (especially for multicore CPU/GPU processors)
including concurrent data structures
** Metaheuristics, for example, tabu search, greedy randomized adaptive
search procedures (grasp), ant colony optimization, multistart methods,
and constraint satisfaction
** Machine learning and statistical techniques
** Data mining techniques

The proposed algorithms should empirically demonstrate efficacy in
solving the targeted EDA problems. When submitting your paper to this
special issue, please include a new section titled "New Algorithmic
Technique(s) Used" that immediately follows the "Introduction"
section, for an explicit identification of the algorithmic
technique(s) used, and a justification, possibly with citations, that
they fit into one of the above categories (a-c). Also, as with any
other journal publication, if the submission is an extension to a
conference paper, please also include a paragraph of justification in
the "Introduction" section (at least 30% new material is required).

SUBMISSIONS

Before submission authors should carefully read over the journal's Author
Guidelines, which are located at

http://www.hindawi.com/journals/vlsi/guidelines/

Prospective authors should submit an electronic copy of their complete
manuscript through the journal Manuscript Tracking System at

http://mts.hindawi.com/

according to the following timetable:

IMPORTANT DATES

Manuscript Due (extended deadline): 30 March 2012
First Round of Reviews: Friday, 15 June 2012
Publication Date Friday: 10 August 2012

FURTHER INFORMATION

Lead Guest Editor:

Shantanu Dutt, dutt@uic.edu, Department of ECE,
University of Illinois at Chicago, Chicago, IL, USA

Guest Editors:

Dinesh Mehta, dmehta@mines.edu, Department of EECS,
Colorado School of Mines, Golden, Co, USA

Gi-Joon Nam, gnam@us.ibm.com, IBM Research Labs, Austin, TX, USA

Back to Contents

Call for Papers: TCAD Special Section on Three-dimensional Integrated Circuits and Microarchitectures

CALL FOR PAPERS: IEEE Transactions on CAD
Special Section on Three-dimensional Integrated Circuits and Microarchitectures

In recent years, the area of three-dimensional (3D) Integrated
Circuits has become a very attractive research topic due to its
potential for extending MooreÕs momentum in the next decade. The key
benefits of 3D ICs over traditional two-dimensional chips include the
potential of reduced overheads for global interconnects, higher
packing densities and smaller footprints, heterogeneous integration,
and faster times-to-market. To efficiently exploit the benefits of 3D
technologies, design techniques and methodologies for supporting 3D
designs are imperative; design space exploration at the architectural
level is also essential to fully take advantage of the 3D integration
technologies to build a high- performance, energy-efficient integrated
systems, GPUs, system-on-chips, heterogeneous systems, and other
integrated systems.

We are pleased to announce a call for papers for a special section of
TCAD on Three-dimensional (3D) Integrated Circuits. We welcome
submissions to this special section based on new, unpublished
contributions. Submissions may also be based on work previously
published in refereed conferences/workshops; if so, the submission
must contain at least 30% new materials, and the authors must provide
a cover letter clearly stating how the submission differs from and/or
expands on the previously-published work.

Areas of interest for this special section include (but are not limited to) the
following topics:

* Physical design methodologies/tools/algorithms for 3D
* High-level synthesis/logic synthesis for 3D ICs
* ESL design methodologies and tools for 3D ICs
* Thermal analysis and thermal-aware designs
* 3D architectures and design space exploration
* 3D Test, design-for-test, and debug techniques
* Signal and power integrity, and ESD in 3D
* Chip-package co-design for 3D
* Economic benefit/cost trade-off studies
* Application, product, or test-chip case studies

Please submit your paper at the TCAD website,

http://mc.manuscriptcentral.com/tcad

Please specify "Special Section on 3D ICs and Microarchitectures" on
your cover page and in the notes section of the Web site submission
form.

IMPORTANT DATES

Submission Deadline: 15 March 2012
Acceptance Notice: 1 July 2012
Final Manuscript Due: 1 August 2012

GUEST EDITORS

Yuan Xie, Pennsylvania State University, yuanxie@cse.psu.edu
Gabriel H. Loh, AMD Research. Gabe.loh@amd.com

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Call for Papers: International Conference on Formal Methods and Models for Codesign (MEMOCODE)

ACM/IEEE Tenth International Conference on Formal Methods and Models for Codesign

MEMOCODE 2012

http://www.memocode-conference.com

Arlington, Virginia
July 16-18, 2012

The goal of MEMOCODE 2012, the tenth in a series of successful
international conferences, is to gather researchers and practitioners
in the field of the design of modern hardware and software system to
explore ways in which future design methods can benefit from new
results on formal methods.

IMPORTANT DATES

Abstract submission deadline: March 9, 2012 (extended)
Paper submission deadline: March 16, 2012 (extended)
Notification of acceptance: May 4, 2012
Final Version for Papers: May 18, 2012

Hardware-software systems face increasing design complexity including
tighter constraints on timing, power, costs, and reliability. MEMOCODE
seeks submissions that present novel formal methods and design
techniques addressing these issues to create, refine, and verify
hardware/software systems. We also invite application-oriented papers,
and especially encourage submissions that highlight the design
perspective of formal methods and models, including success stories
and demonstrations of hardware/software codesign. Furthermore, we
invite poster presentations describing ongoing work with promising
preliminary results.

Topics of interest for regular submissions include but are not limited to

* system- and transaction-level modeling and verification, abstraction
and refinement between different modeling levels, formal,
semi-formal, and specification-driven verification,

* design and verification methods for composition of concurrent
systems: multi-core platform architectures, systems-on-chip,
networks-on-chip,

* formal methods and tools for hardware and software verification
including theorem proving, decision procedures,

* non-traditional and domain-specific design languages for hardware
and software, novel models of computation, and new design paradigms
that unify hardware and software design,

* system-level estimation of performance and power in heterogeneous
hardware/software architectures,

* applications and demonstrators of formal design methodologies and
case studies of innovative system-level design flows,

* modeling and reuse of intellectual property at system-level, and

* design abstraction and high-level design demonstrating productivity
and quality in generating and validating RTL and software.

PROCEEDINGS

Conference proceedings will be published by the IEEE Computer Society.

SUBMISSION

Submissions of research and experience papers will only be accepted
through the conference website. Papers must not exceed 10 pages and
must be formatted following IEEE Computer Society guidelines.
Submissions must be written in English, describe original work, and
not substantially overlap papers that have been published or are being
submitted to a journal or another conference with published
proceedings. Poster submissions should consist of an abstract of at
most 250 words. The abstract will be distributed to the conference
attendants but will not be published. Note that the poster deadline is
different from the paper deadline.

SUBMISSION WEBSITE: http://www.easychair.org/conferences/?conf=memocode2012

DESIGN COMPETITION: MEMOCODE will again have a design contest. This
year's problem for the design contest is part of the DNA sequence
alignment problem: exact substring matching. The challenge is to
efficiently locate millions of 100-base-pair short read sequences in a
3-million-base-pair reference genome. Good solutions will combine
judicious algorithm design with carefully designed data-handling
architecture. The contest starts March 1, 2012. The deadline for
submission is April 1st, 2012 and the notification of the results is
on May 13, 2012. The conference will sponsor at least two prize
categories, each with a significant monetary award (each of the two
categories was awarded a $1000 prize in 2010). Each team delivering a
complete and working entry will be invited to submit for review a
2-page abstract for the formal conference proceedings and present a
poster at the conference. Winning teams will be invited to contribute
a 4-page short paper and present their work at the conference. Please
refer to the website for more information and updates.

SPONSORS: IEEE CEDA, IEEE CAS, ACM SIGBED, and ACM SIGDA.

ORGANIZING COMMITTEE

General Chair
Sandeep Shukla (Virginia Tech)

Program Chairs
Luca Carloni (Columbia)
Daniel Kroening (Oxford)

Design Contest Chair
Stephen A. Edwards (Columbia)

Finance Chair
James Hoe (CMU)

Publication Chair
Jens Brandt (TU Kaiserslautern)

PROGRAM COMMITTEE

Roderick Bloem (Graz)
Luca Carloni (Columbia)
Abhijit Davare (Intel)
Robert de Simone (INRIA)
Stephen A. Edwards (Columbia)
Franco Fummi (Verona)
Thierry Gautier (INRIA)
Alain Girault (INRIA)
David Greaves (Cambridge)
Daniel Grosse (Bremen)
Connie Heitmeyer (NRL)
Franjo Ivancic (NEC Labs)
Barbara Jobstmann (CNRS)
Michael Kishinevsky (Intel)
Christoph Kirsch (Salzburg)
Daniel Kroening (Oxford)
Luciano Lavagno (Torino)
Elizabeth Leonard (NRL)
John O'Leary (Intel)
Philip Ruemmer (Uppsala)
Klaus Schneider (Kaiserslautern)
Satnam Singh (Google)
Jean-Pierre Talpin (INRIA)
Michael Theobald (D. E. Shaw)
Shobha Vasudevan (UIUC)
Thomas Wahl (Northeastern)
Fei Xie (Portland)
Qi Zhu (UC Riverside)

STEERING COMMITTEE

Arvind (MIT)
Masahiro Fujita (University Tokyo)
Rajesh Gupta (UC San Diego)
Connie Heitmeyer (NRL)
James Hoe (CMU)
Sandeep Shukla (Virginia Tech)
Jean-Pierre Talpin (INRIA)

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Call for Papers: International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

CALL FOR PAPERS

RTCSA 2012
The 18th IEEE International Conference on Embedded and Real-Time
Computing Systems and Applications

http://rtcsa.konkuk.ac.kr/

August 20 - 22, 2012
Seoul, Korea

SUBMISSION DEADLINE: Apr 16, 2012, 12:00 (noon) GMT+9

Embedded software has become a necessity in almost every aspect of the
daily lives of individuals and organizations, from self-contained
applications to those embedded in various devices and services (mobile
phones, vital sign sensors, medication dispensers, home appliances,
engine ignition systems, etc). A large proportion of these systems
are mission/life critical and performance sensitive.

The 18th IEEE International Conference on Embedded and Real-Time
Computing Systems and Applications (RTCSA 2012) will bring together
researchers and developers from academia and industry for advancing
the technology of embedded and real-time systems, and ubiquitous
computing applications. The conference has the following goals: to
investigate advances in embedded and real-time systems and ubiquitous
computing applications; to promote interaction among the areas of
embedded computing, real-time computing and ubiquitous computing; to
evaluate the maturity and directions of embedded and real-time system
and ubiquitous computing technology. RTCSA 2012 invites submissions
of papers presenting a high quality original research and development
for the conference tracks: (1) Embedded Systems, (2) Real-time
Systems, and (3) Ubiquitous Computing/Cyber-physical Systems.

SCOPES: Following the tradition of RTCSA, the conference has three
tracks: embedded systems, real-time systems, and ubiquitous computing.
The topics of interest include, but are not limited to:

EMBEDDED SYSTEMS TRACK:
- System level design and HW/SW co-design
- Embedded system design practices
- Operating systems and scheduling
- Software and compiler issues for heterogeneous multi-core embedded
platform
- Embedded system architecture
- Networks-on-chip design
- Power/thermal-aware design issues
- Memory issues for multi-core embedded platform
- Hardware and software techniques for fault tolerance
- Reconfigurable computing architecture and software support

REAL-TIME SYSTEMS TRACK:
- Real-time operating systems
- Real-time scheduling
- Timing analysis
- Databases
- Programming languages and run-time systems
- Middleware systems
- Design and analysis tools
- Communication networks and protocols
- Case studies and applications
- Media processing and transmissions
- Real-time aspects of Wireless sensor networks
- Energy aware real-time methods

UBIQUITOUS COMPUTING/CYBER-PHYSICAL SYSTEMS TRACK:

- Real-time issues in ubiquitous computing and cyber-physical systems
- Tools, infrastructures and architectures for ubiquitous computing
and cyber-physical systems
- Devices and enabling technologies for ubiquitous computing and
cyber-physical systems
- Design and verification methodologies for cyber-physical systems
- Applications of wireless sensor networks
- Ubiquitous computing applications
- Cyber-physical systems applications
- User interfaces and interaction design issues for ubiquitous computing
- Privacy and security issues and implications of ubiquitous computing
- Location-dependent and context-aware computing
- Evaluation methods for ubiquitous computing devices, systems, and
applications

Regular Paper Submission:

The submitted manuscript must describe original work not previously
published and not concurrently submitted elsewhere. Submissions
should be no more than 10 pages in IEEE conference proceedings format
(two-column, single-space, 10pt). The prospective authors should
submit their papers on RTCSA 2012 paper submission site:
http://www.rtcsa.org (in preparation for now)

Work-in-Progress Session:

This session provides an opportunity for researchers attending RTCSA
to present and discuss their research. This one hour event will
feature concurrent short presentations by all participants organized
in poster formats. More detailed information is available on the web.

IMPORTANT DATES:

Paper Submission: Apr 16, 2012, 12:00 (noon) GMT+9
Acceptance Notification: May 23, 2012
Camera Ready Submission: June 3, 2012

WIP Abstract Submission: June 18, 2012
WIP Notification: June 22, 2012
WIP Camerca Ready Submission: July 13, 2012

Early Registration Deadline: June 24, 2012

ORGANIZING COMMITTEE:

Steering Committee:
Tatsuo Nakajima, Waseda University, Japan (Chair)
Tei-Wei Kuo, National Taiwan University, Taiwan
Joseph K. Ng, Hong Kong Baptist University, China
Hide Tokuda, Keio University, Japan
Seongsoo Hong, Seoul National University, Korea
Sang H. Son, University of Virginia, USA

General Co-Chairs:
Yunheung Paek, Seoul National University, Korea
Jorgen Hansson, Chalmers University, Sweden

Program Co-Chairs:
Real-Time Systems: Steve Goddard, University of Nebraska-Lincoln, USA
Ubiquitous Comp/Cyber-Physical Systems: Chin-Fu Kuo, National University
of Kaohsiung, Taiwan
Embedded Systems: Jongeun Lee, UNIST, Korea

WIP Chair:
Chang-gun Lee, Seoul National University, Korea
Shinpei Kato, UC Santa Cruz, USA

Financial Chair:
Hyeonsang Eom, Seoul National University, Korea

Local Arrangement Chair:
Sung-Soo Lim, Kookmin University, Korea

Publication Chair:
Jangwoo Kim, Postech, Korea

Web Chair:
Neungsoo Park, Kunkuk University, Korea

Publicity Co-Chairs:
Thomas Nolte, Malardalen University, Sweden (Europe)
Yoshinori Takeuchi, Osaka University, Japan (Asia)
Sudeep Pasricha, Colorado State University, USA (USA)

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Call for Papers: International Symposium on Low Power Electronics and Design (ISLPED)

CALL FOR PAPERS - ISLPED 2012 (http://www.islped.org)

IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN

Location: Redondo Beach, CA, USA
Date: July 30-August 1, 2012

****IMPORTANT DATES****

Abstract submission deadline: March 2, 2012
Technical paper submission deadline: March 9, 2012
Notification of paper acceptance: April 20, 2012
Camera-ready version due: May 20, 2012

Electronics advances especially in mobile applications require
significant reductions in power, and this is a critical area for the
design of electronic circuits and systems. The International
Symposium on Low Power Electronics and Design (ISLPED) is the premier
forum for presentation of recent advances in all aspects of low power
design and technologies, ranging from process and circuit
technologies, simulation and synthesis tools, to system level design
and optimization.

Specific topics include, but are not limited to, the following two main
areas, each with three sub-areas:

1. Architecture, Circuits, and Technology
1.1. Technologies and Digital Circuits
1.2. Logic and Microarchitecture Design
1.3. Analog, MEMS, Mixed Signal and Imaging Electronics

2. Design Tools, System and Software Design
2.1. CAD & Design Tools
2.2. System Design and Methodologies
2.3. Software Design and Optimization

The scope of the Symposium includes innovative techniques in the following
areas:
- Process Technologies and new devices for ultra-low power systems
- Digital circuit techniques in deeply scaled technologies
- Clock generation and distribution to enable reduced power
- Ultra-low power memory circuits, including novel non-volatile memories
- Power circuits, linear and switching regulators and voltage references
- Enabling technologies for >100x power reduction in "More than Moore"
- Logic and microarchitecture design for reduction of power
- Optimization of power and performance at microarchitecture and system levels
- Analog and mixed signal circuits such as data converters and amplifiers
- Design Tools, System, and Software Design for ultra-low power optimization.
- Tools and methodologies that enable orders of magnitude power reduction
- Complex SOC systems that show significant reduction in power.
- Power minimization techniques for analog and digital circuits, including
novel energy harvesting, battery management and renewable energy topics.
- Battery technologies and energy generation and management for ultra-low
power systems, including wireless sensor nodes, low-power display systems,
actuators, imaging, and motor drives.
- Techniques for digitally-assisted analog and analog-assisted digital that
show significant power reduction over more traditional techniques.

****TECHNICAL PAPER SUBMISSIONS****

Submissions should be full-length papers of up to 6 pages
(double-column format, font size 9pt to 10pt), including all
illustrations, tables, references and an abstract of no more than 100
words. Papers exceeding the six-page limit will not be reviewed.
Submission must be anonymous: papers identifying the authors will be
automatically rejected.

Electronic submission in pdf format only via the web is required.
More information on electronic submission to ISLPED'12 can be found at
http://www.islped.org/.

ORGANIZING COMMITTEE:

General Co-Chairs
-Massimo Poncino, Politecnico di Torino
-Naresh Shanbhag, UIUC

TPC Co-Chairs
-Pai Chou, UC Irvine
-Ajith Amerasekara, Texas Instruments

Local Arrangement Chair
-Puneet Gupta, UCLA

Treasurer
-Yuan Xie, Penn State Univ.

Publicity Co-Chairs
-Luca Benini, Università di Bologna
-John Donovan (Low Power Design)

Design Contest Chair
-Chia-Lin Yang, National Taiwan Univ.

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Call for Papers: JETC Special Issue on Reliability and Device Degradation in Emerging Technologies

Call for Papers
JETC Special Issue on Reliability and Device Degradation in Emerging Technologies

In recent years, reliability has emerged as a critical metric for
semiconductor technologies. Temporal changes in device and system
performance due to physical and environmental effects are resulting in
larger design margins, increased test costs and increased number of
in-field failures. In order to understand these problems, and
potential solutions, we are pleased to announce a call for papers for
a special issue of the ACM Journal on Emerging Technologies in
Computing Systems on reliability and device degradation in emerging
technologies

This special issue will focus on the reliability, aging and robustness
of devices, circuits and systems in emerging technologies. Of
particular interest is innovations with nanotechnology and
non-traditional Si CMOS.

Topics of interest include, but are not limited to:

Device reliability and degradation modeling and simulation New aging
and reliability phenomena associated with new device structures Design
methodologies for improved reliability Memory cell and sub system
reliability Reconfigurable systems reliability New devices
sensitivities to SER and upset events CAD tools and simulation engines
aimed at reliability

Information about JETC, including instructions for manuscript
preparation, is available at http://jetc.acm.org. Please submit your
manuscript electronically at http://mc.manuscriptcentral.com/jetc, and
indicate “Special Issue on “Reliability and Device Degradation in
Emerging Technologies” on the cover page and in the notes section of
the submission form. Manuscripts must conform to the JETC style
(double-spaced in 10-point font), and be limited to 20 pages for
research papers, and 40-50 pages for tutorial and survey papers.
Expanded versions of previously published conference research papers
are welcome as long as they contain at least 30% new material; authors
should clearly state in a footnote on the first page how the
manuscript differs from the conference paper. Papers simultaneously
submitted elsewhere may be returned without review. Longer papers can
be considered upon request and at the discretion of the
Editor-in-Chief.

Important Dates:

Submission Deadline: March 15, 2012
Author Notification: June 1, 2012
Revised Manuscripts Due: July 1, 2012
Notice of Final Acceptance: August 1, 2012
Final Manuscripts Due: September 15, 2012
Publication Date: January 2013

GUEST EDITORS:

Dr. Rahul M. Rao
Watson Research Center
IBM Research
raorahul@us.ibm.com

Dr. Fadi H. Gebara
Austin Research Lab
IBM Research
fhgebara@us.ibm.com

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Call for Papers: International Workshop on Logic & Synthesis (IWLS)

Call for Papers
The 21th International Workshop on Logic & Synthesis
sponsored by the ACM/SIGDA and by the IEEE
June 1 - 3, 2012
University of California, Berkeley
Co-located with the Design Automation Conference
website: http://www.iwls.org

The International Workshop on Logic and Synthesis is the premier
forum for research in synthesis, optimization, and verification
of integrated circuits and systems. Research on logic synthesis
for emerging technologies and for novel computing platforms, such
as nanoscale systems and biological systems, is also strongly
encouraged. The emphasis is on novelty and intellectual rigor.
The workshop encourages early dissemination of ideas and results.
The workshop accepts complete papers as well as abstracts,
highlighting important new problems in the early stages of
development, without providing complete solutions.

Topics of interest include (but are not limited to): synthesis
and optimization; power and timing analysis; testing, validation
and verification; architectures and compilation; and design
experiences. Submissions on modeling, analysis and synthesis for
emerging technologies and platforms are particularly encouraged.

Both complete papers as well as extended abstracts highlighting
new problems and new topics of research are welcomed. Only
original and previously unpublished material is permitted.
Submissions must be no longer than 8 pages, double column,
10-point font. Accepted papers are distributed only to IWLS
participants.

The workshop format includes paper presentations, posters, invited
talks, social lunch and dinner gatherings, and recreational
activities. Submissions are made electronically through the EDAS
system. Please see the website for instructions: http://www.iwls.org

Abstract submission: March 9, 2012
Submission deadline for papers: March 16, 2012 - 11.59pm HAST
Notification of acceptance: April 2, 2012
Final version due: May 5, 2012

************************************************************
*** The submission deadline of March 16, 2012 is final, ****
**** there will be no extension. ****
************************************************************

For questions, contact: Ilya Wagner (email: ilya.wagner@intel.com)

We are striving offer heavily discounted registration rates for
students and unemployed attendees. In addition, attendees who plan to
attend both IWLS and DAC will have higher priority for the several
travel support opportunities provided through DAC.

General Chair:
Ilya Wagner, Intel

Program Chair:
Philip Brisk, University of California, Riverside

Special Sessions Chair:
Andrea Pellegrini, University of Michigan

Local Arrangements Chair:
Alan Mishchenko, University of California, Berkeley

Special Activities Chair:
Tobias Welp, University of California, Berkeley

Executive Committee:
Valeria Bertacco, University of Michigan
Igor Markov, University of Michigan

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Call for Participation: International Symposium on Physical Design (ISPD)

Call for Participation

ACM International Symposium on Physical Design 2012
With a tribute to Prof. C.-L. Liu
http://www.ispd.cc

Location: Napa California, USA
Sponsored by ACM SIGDA with Technical Co-sponsorship from IEEE CAS

The International Symposium on Physical Design (ISPD) provides a
premier forum to exchange ideas and promote research on critical areas
related to the physical design of VLSI systems. ISPD-2012 will be held
March 25-28, 2012 in Napa, California.

The 2012 technical program is now available at
http://ispd.cc/ispd12_program.html. Registeration can be made from
the conference website. For information about travel and accomodation,
please also visit the conference website.

SYMPOSIUM ORGANIZATION

General Chair: Jiang Hu (Texas A&M Univ.) [jianghu@ece.tamu.edu]
Steering Committee Chair: Yao-Wen Chang (National Taiwan Univ.) [ywchang@cc.ee.ntu.edu.tw]
Technical Program Chair: Cheng-Kok Koh (Purdue Univ.) [chengkok@purdue.edu]
Publications Chair: Cliff Sze (IBM) [csze@us.ibm.com]
Publicity Chair/Webmaster: Azadeh Davoodi (Univ. Wisconsin) [adavoodi@wisc.edu]

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Call for Participation: Ph.D. Forum at DAC

Ph.D. Forum at DAC

Call for Participation

The Ph.D. Forum at the Design Automation Conference is a poster
session hosted by SIGDA for Ph.D. students to present and discuss
their dissertation research with people in the EDA community. It has
become one of the premier forums for Ph.D. students in design
automation to get feedback on their research and for industry to see
academic work in progress: 400 - 500 people attended the last
forums. Participation in the forum is competitive with acceptance rate
of around 30%. Limited funds will be available for travel assistance,
based on financial needs. The forum is open to all members of the
design automation community and is free-of-charge. It is co-located
with DAC, that is held in June 3-7, to attract the large DAC audience,
but DAC registration is not required in order to attend this event.

Contact Information

For questions not addressed on this page, please send e-mail
Dr. Shiyan Hu: shiyan@mtu.edu. Please include "DAC Ph.D. Forum" in the
subject line of your email.

Eligibility

* Students with at least one published or accepted conference,
symposium or journal paper.
* Students within 1-2 years of dissertation completion and students
who have completed their dissertation during the 2011-2012 academic
year.
* Dissertation topic must be relevant to the DAC community.
* Previous forum presenters are not eligible.
* Students who have presented previously at the DATE and ASP-DAC
Ph.D. forums are eligible, but will be less likely to receive travel
assistance.

Important Dates

* Submission Deadline: Monday, March 15, 2012, 5:00PM MDT
* Notification Date: TBA

Submission Requirements

* A two-page PDF abstract of the dissertation (in two-column format,
using 10-11 pt. fonts and single-spaced lines), including name,
institution, advisor, contact information, estimated (or actual)
graduation date, whether the work has been presented at ASP-DAC
Ph.D. Forum or DATE Ph.D. Forum, as well as figures, and
bibliography (if applicable). The two-page limit on the abstract
will be strictly enforced: any material beyond the second page will
be truncated before sending to the reviewers. Please include a
description of the supporting paper, including the publication
forum. A list of all papers authored or co-authored by the student,
related to the dissertation topic and included in the two-page
abstract, will strengthen the submission.
* A published (or accepted) paper, in support of the submitted
dissertation abstract. The paper must be related to the dissertation
topic and the publication forum must have a valid ISBN number. It
will be helpful, but is not required, to include your name and the
publication forum on the first page of the paper. Papers on topics
unrelated to the dissertation abstract or not yet accepted will not
be considered during the review process. Please Note:
* The abstract is the key part of your submission. Write the abstract
for someone familiar with your technical area, but entirely
unfamiliar with your work. Clearly indicate the motivation of your
Ph.D. dissertation topic, the uniqueness of your approach, as well
as the potential impact your approach may have on the topic.
* In the beginning of the abstract, please indicate to which track
your submission belongs.
* Proper spelling, grammar, and coherent organization are critical:
remember that the two pages may be the only information about
yourself and your PhD research available to the reviewers.
* All submissions must be made electronically through EasyChair
system.
* Please include the supporting paper with the abstract in one PDF
file and submit the single file. There are many free utilities
available online which can merge multiple PDF files into a single
file if necessary.

Tracks

1. System-level Design, Synthesis and Optimization (including
network-on-chip, system-on-chip and multi/many-core, HW/SW
co-design, embedded software issues, modeling and simulation
2. High Level Synthesis, Logic Level Synthesis
3. Physical Design and Manufacturability
4. Power and Reliability Analysis and Optimization (including power
management from system level to circuit level, thermal management,
process variability management)
5. Timing Analysis, Circuit and Interconnect Simulation
6. Signal Integrity and Design Reliability, Analog/Mixed Signals and RF
7. Verification, Testing, Pre- and Post-Silicon Validation, Failure
Analysis
8. Reconfigurable and Adaptive Systems
9. Emerging Design and Technologies (carbon nano-tubes, molecular
electronics, MEMS, micro-fluidic system, biologically-inspired
systems, quantum computing, etc.)

Submissions dealing with power modeling, analysis, and/or optimization
may be submitted to any track, depending on the abstraction level and
contents of the work. Same principle also applies to variability-aware
and fault-tolerant design and analysis. Please consult your advisor to
determine which track is the best fit for your submission. If you
still have questions about the most appropriate submission track, you
are encouraged to contact the TPC Chair, Dr. Gayatri Mehta
(Gayatri.Mehta@unt.edu).

Contact Information

For questions not addressed on this page, please send e-mail
Dr. Shiyan Hu: shiyan@mtu.edu. Please include "DAC Ph.D. Forum" in the
subject line of your email.

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Call for Papers: International Conference on Very Large Scale Integration (VLSI-SOC)

20th IFIP/IEEE International Conference on Very Large Scale Integration
VLSI-SoC 2012
October 7-10, 2012
Santa Cruz, CA, USA
Dream Inn Hotel

http://www.vlsi-soc.com

VLSI-SoC 2012 is the 20th in a series of international conferences
sponsored by IFIP TC 10 Working Group 10.5, IEEE CEDA and IEEE CASS
that explores the state-of-the-art and the new developments in the
field of Very Large Scale Integration (VLSI) and System-on-Chip
(SoC). Previous Conferences have taken place in Edinburgh, Trondheim,
Tokyo, Vancouver, Munich, Grenoble, Gramado, Lisbon, Montpellier,
Darmstadt, Perth, Nice, Atlanta, Rhodes, Florianopolis, Madrid and
Hong Kong. The purpose of VLSI-SoC is to provide a forum to exchange
ideas, and show academia/industrial research results in the fields of
VLSI/ULSI Systems, SoC design, VLSI CAD and Microelectronic Design and
Test.

Topics of interest include but are not limited to:
* Analog and Mixed-Signal IC Design
* Circuits and Systems for Micro-sensing Applications
* 3-D Integration, Physical Design, Compact Modeling, and
Electromagnetic Analysis
* Design for Variability, Reliability, Fault Tolerance, Test
* Digital Signal Processing and Image Processing IC Design
* New Devices, MEMS and Microsystems
* Prototyping, Validation, Verification, Modeling and Simulation
* System-On-Chip Design, Digital Architectures
* Embedded Systems Design and Real-Time Systems
* Reconfigurable Systems, Compiler
* Logic and High-Level Synthesis
* Low-Power and Thermal-aware Design

PAPER SUBMISSION

Papers should present original research results not published or
submitted for publication in other forums. Electronic submission in
PDF format to the http://www.vlsi-soc.com web site is required. The
proceedings will be published by IEEE and available through IEEE
Xplore. They will be distributed during the conference to all
participants. A selection of the conference best papers will be
invited to submit an extended version to be included as chapters of a
book to be published by Springer.

Paper Submission Deadline: April 9, 2012
Special Session Proposal/Papers: April 23, 2012
Notification of acceptance: June 17, 2012
Camera-ready: July 11, 2012

PAPER FORMAT

Papers should not exceed 6 pages (single-spaced, 2 columns, 10pt
font).Submissions should be in camera-ready, following the IEEE
proceedings specifications located at:
http://www.ieee.org/web/publications/pubservices/confpub/AuthorTools/conferenceT...

PAPER PUBLICATION AND PRESENTER REGISTRATION

Papers will be accepted for regular or poster presentation at the
conference. Every accepted paper MUST have at least one author
registered to the conference by the time the camera-ready paper is
submitted; the author is also expected to attend the conference and
present the paper. A limited number of travel grants are available to
needy PhD students. Please see the web site for more information.

PHD FORUM

The VLSI-SoC 2012's Ph.D. Forum is a poster session dedicated to the
exchange of ideas and experiences of Ph.D. students from different
parts of the world. Elected Ph.D. students have an opportunity to
discuss their thesis and research work with specialists within the
system and design automation communities. This exchange offers a good
opportunity for students to receive valuable feedback and gain
exposure in the job market. Furthermore, this forum also provides a
great chance for industry officials to meet junior researchers, giving
an avenue for incorporating the latest research developments into
their companies. More information in the conference web page.

ORGANIZING COMMITTEE:

General Chair:
Matthew Guthaus, UC Santa Cruz, USA

Program Chairs:
Ayse Coskun, Boston Univ., USA;
Andreas Burg, EPFL, Switzerland

Special Sessions Chair:
Sung-Mo "Steve" Kang, UC Santa Cruz, USA
Jose Renau, UC Santa Cruz, USA

Local Arrangement Chair:
Jose Renau, UC Santa Cruz, USA

Publication Chairs:
Srinivas Katkoori, Univ of South Florida, USA;
Ricardo Reis, UFRGS, Brazil

Publicity Chair:
Ricardo Reis, UFRGS, Brazil

Registration Chair:
Rajsaktish Sankaranarayanan, UC Santa Cruz, USA

Finance Chair:
Baris Taskin, Drexel, USA

PhD Forum Chair:
Ken Pedrotti, UC Santa Cruz, USA

Steering Committee:
Manfred Glesner, TU Darmstadt, Germany;
Salvador Mir, TIMA, France;
Ricardo Reis, UFRGS, Brazil;
Michel Robert, U. Montpellier, France;
Luis Miguel Silveira, INESC ID, Portugal

Sponsored by
IEEE Computer Society

Back to Contents

Call for Papers: Special Issue on Practical Parallel EDA

Call for Papers
IEEE Design & Test of Computers
Special Issue on Practical Parallel EDA

Guest Editors: Rasit O. Topaloglu (IBM) and Bevan M. Baas (University of California, Davis)

It is clear that future advances in computing performance will not be
driven by increases in individual core performance but rather by
factors such as an increasing number of available processors, or
specialized hardware. Thus, successful electronic design automation
(EDA) engineers and software developers must become familiar with
parallel algorithms and methods to exploit parallel and specialized
computing resources. Sequential EDA algorithms of the past are not
keeping pace with increasing design complexity—hence the striking need
to apply parallel computing methods to EDA problems.

Execution of software on parallel computing platforms requires a
re-engineering of EDA tools that are used during VLSI design. While
there are experts in various domains of parallelism, the knowledge has
yet to be dispersed widely and utilized in various EDA
tools. Attaining knowledge in parallelism requires one to understand
it from many aspects—for example, not only are parallel algorithms
typically different than serial ones, but the programming methods and
tools are also often signiﬁcantly different. The availability of low
cost parallel processing hardware has made this transformation both
possible and increasingly relevant.

IEEE Design and Test Magazine is seeking contributions for a special
issue to educate engineers and present recent work in the area of
practical parallelism in EDA. Algorithm implementation can target
various parallel architectures such as: graphical processing units
(GPUs), multicore CPUs, manycore CPUs, distributed systems, advanced
processing units, and FPGAs. We also encourage submission of papers
that point to practical limitations of parallelism in EDA. Topics of
interest include but are not limited to:

* Parallel algorithms for electronic design automation
* Performance comparison of parallel programming methods for EDA algorithms2
* Performance comparison of parallel architectures for a given EDA
algorithm or set of algorithms.
* Performance comparison of EDA algorithms or set of algorithms
implemented on a variety of parallel architectures.
* Tips and tricks of parallel implementation from a real product
* User perspectives from parallel EDA software users
* Practical limitations of parallel EDA algorithm implementations
* Cost and beneﬁt analysis of parallel EDA

SUBMISSION AND REVIEW PROCEDURES

Prospective authors should follow the submission guidelines for IEEE
Design & Test. All manuscripts must be submitted electronically to the
IEEE Manuscript Central Web site at
https://mc.manuscriptcentral.com/cs-ieee . Indicate that you are
submitting your article to the special issue on Practical Parallel
EDA. All articles will undergo the standard IEEE Design & Test review
process. Submitted manuscripts must not have been previously published
or currently submitted for publication elsewhere. Manuscripts must not
exceed 5,000 words, including ﬁgures (with each average-size ﬁgure
counting as 200 words) and a maximum of 12 References (50 for
surveys). This amounts to about 4,000 words of text and a maximum of
ﬁve small to medium ﬁgures. Accepted articles will be edited for
clarity, structure, conciseness, grammar, passive to active voice,
logical organization, readability, and adherence to style. Please see
IEEE Design & Test Author Resources at
http://www.computer.org/dt/author.htm, then scroll down and click on
Author Center for submission guidelines and requirements.

SCHEDULE

Articles due 4/15/2012
Reviews due 6/15/2012
Revisions due 7/15/2012
Final version due 9/1/2012
Publication 1-2/2013

Back to Contents

Call for Papers: Foundations and Trends in Electronic Design Automation (FnTEDA)

Foundations and Trends in Electronic Design Automation (FnTEDA) is
proud to announce Professor Radu Marculescu of Carnegie Mellon
University as its new editor-in-chief, effective January 1, 2012. He
succeeds the founding editor-in-chief, Professor Sharad Malik of
Princeton University.

Under Professor Malik's guidance FnTEDA has carved out an important
niche in the existing literature, publishing high-quality
peer-reviewed surveys, reviews and tutorials. We thank him for his
achievements and look forward to continuing success with Professor
Marculescu at the helm.

Foundations and Trends in Electronic Design Automation is different to
most scientific journals. Its aim is not to publish new results, but
up-to-date high-level interpretations (which may be new) of (usually)
recent work, in a survey and/or tutorial style. Review articles are
traditionally the most cited and used articles in the scientific
literature. FnTEDA articles are published upon acceptance which
further enhances their value. Moreover, FnTEDA authors retain
copyright and are free to post the published versions on their
websites. If you are interested in proposing an article, please
contact Radu Marculescu (radum@cmu.edu) or the publisher, James Finlay
(james.finlay@nowpublishers.com). See www.nowpublishers.com/eda for
more information.

Back to Contents

Call for Papers: International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

Preliminary Call for Papers

CODES+ISSS 2012

http://codes-isss.org/ and http://codes-isss.snu.ac.kr

International Conference on Hardware/Software Codesign and System Synthesis

The International Conference on Hardware/Software Codesign and System
Synthesis(CODES+ISSS) is the premier event in design, modeling,
analysis, and implementation of modern embedded systems, from
system-level analysis and optimization to hardware/software
implementation. The conference is a forum for active discussion of
topics of current and future importance to designers and
researchers. The program will bring together the latest in academic
and industrial research and development. High-quality original papers
will be accepted for oral presentation followed by interactive poster
sessions. CODES+ISSS 2012 is part of the Embedded Systems Week 2012.

Program chairs:
Prof. Naehyuck Chang, Seoul National University (naehyuck@elpl.snu.ac.kr)
Prof. Franco Fummi, University of Verona (franco.fummi@univr.it)

Important Dates

* Abstract submission: March 28, 2012
* Full paper submission: April 04, 2012
* Notification of acceptance: July 03, 2012
* Camera-ready version: July 31, 2012
* Conference: October 7-12, 2012 (Tampere, Finland)

Areas of Interest

The CODES+ISSS invites papers on the specification, modeling, design,
analysis, and implementation designs from embedded systems to systems
of systems. The conference covers range of design problems and
applications relevant to important embedded system quality metrics
including performance, cost, power consumption, reliability, security,
usability, and compactness. Each paper is supposed to tackle new
challenges based on new novel and innovative idea and/or emerging
technologies. The following area of topics are welcomed but not
limited to:

Track 1) Hardware/software co-design - Specification and refinement,
design representation, system synthesis, partitioning,
hardware-software interaction/interface, design space
exploration, reconfigurable design, and model-based design.
Track 2) Domain and application-specific design techniques - Analysis,
design, and automation techniques for multimedia, medical,
automotive, security, and other specialized application
domains.
Track 3) Embedded software - Compilers, memory management, virtual
machines, scheduling, operating systems, real-time support,
fault-tolerance, and middleware.
Track 4) Embedded systems architecture - Architecture and
micro-architecture design, exploration and optimization
including application-specific, storage systems, memory and
communication.
Track 5) Large-scale system architecture - Multi-core, GPU,
heterogeneous systems, system-level communication, and
networks-on-chip architectures.
Track 6) Systems of systems - Design and optimization of data centers,
cloud computing, heterogeneous embedded systems,
cyber-physical systems, etc.
Track 7) Simulation, validation and verification - Hardware/software
co-simulation, verification and validation methodologies,
formal verification, hardware-accelerated simulation, test
methodology, design for testability, specification
languages/models, and benchmarks.
Track 8) Power-aware systems - Power- and energy-aware system design
and methodologies ranging from low-power embedded systems to
energy-efficient large scale systems such as Green IT and
Smart Grid.
Track 9) Industrial practices and case studies - Practical impacts on
current and/or future industries with applications of the
state-of-the-art methodologies and tools in various
application areas including wireless, networking, multimedia,
automotive, medical systems, sensor networks, etc.

Submission Information

* Papers should represent original work, not published or submitted
for publication in other forums.

* A blind review process will be enforced. Authors should not reveal
authorship directly or indirectly through references.

* Papers must be in PDF format and should not exceed 10 pages in ACM
two-column format (9pt on 8.5"x11" letter size paper). For formatting
instructions and templates, visit the ACM web site. 10 pages is an
upper limit. Authors are encouraged to submit shorter (e.g., 6 pages)
papers if this better fits the nature and content of the paper.

* Formal proceedings will be published on CD-ROM and web page forms
(copyright by ACM and IEEE).

Back to Contents

Call for Papers: Embedded Systems Week

Call for Papers
EMBEDDED SYSTEMS WEEK
Tampere, Finland, October 7-12, 2012
www.esweek.org

News: ESWeek 2012 will be co-located with SoC 2012

About ESWeek

ESWeek is a premier event covering all aspects of embedded systems and
software. It brings together conferences, tutorials, and workshops
centered on various aspects of embedded systems research and
development. Three leading conferences in the area - CASES,
CODES+ISSS, and EMSOFT - will take place at the same time and
location, allowing attendees to benefit from a wide range of topics
covered by these conferences and their associated tutorials and
workshops.

Dates

- Abstract submission: March 28, 2012
- Full paper submission: April 04, 2012
- Acceptance notification: July 03, 2012
- Camera ready version: July 31, 2012
- Conference: October 7-12, 2012

For paper submission instructions see: www.esweek.org

Organization

ESWeek General Chairs:
Ahmed Jerraya, CEA, France
Luca Carloni, Columbia University, USA

ESWeek Local Arrangement Chairs:
Jari Nurmi, Tampere University of Technology, Finland

CASES TPC Chairs:
Vincent Mooney, Georgia Institute of Technology, USA
Rodric Rabbah, IBM, USA

CODES+ISSS TPC Chairs:
Franco Fummi, University of Verona, Italy
Naehyuck Chang, ELPL, Seoul National University, Korea

EMSOFT TPC Chairs:
Florence Maraninchi, Verimag, Grenoble INP, France
John Regehr, School of Computing, University of Utah, USA

Back to Contents

Call for Abstracts: International Workshop on Bio-Design Automation (IWBDA)

CALL FOR ABSTRACTS

The Fourth International Workshop on Bio-Design Automation (IWBDA 2012)
San Francisco, June 3-4, 2012
http://www.biodesignautomation.org

The International Workshop on Bio-Design Automation (IWBDA) brings
together researchers from the synthetic biology, systems biology, and
design automation communities. The focus is on concepts,
methodologies, and software tools to enable the computational analysis
of biological systems and the synthesis of novel biological functions.

Tracks of interest include:

Design methodologies for synthetic biology
Standardization of biological components
Automated assembly techniques
Computer-aided modeling and abstraction techniques
Engineering methods inspired by biology
Domain specific languages for synthetic biology
Data exchange standards and models for synthetic biology

The workshop will be held at the Moscone Center in San Francisco on
June 3rd - 4th, 2012, co-located with the Design Automation Conference
(DAC). Registration information will be posted on the workshop
webpage: http://www.biodesignautomation.org. For questions, please
email info@biodesignautomation.org

ABSTRACT SUBMISSION:

Abstracts should be two pages long, following the ACM SIG Proceedings
templates at
http://www.acm.org/sigs/publications/proceedings-templates. Indicate
whether you would like your abstract considered for a poster
presentation, an oral presentation, or both. Include the full names,
affiliations and contact information of all authors.

Abstracts will be reviewed by the Program Committee. Those that are
selected for oral and poster presentations will distributed to
workshop participants and posted on the workshop website.

Abstracts should be submitted by April 2nd at:
http://www.easychair.org/conferences/?conf=iwbda2012

Journal Special Issue
As in years past, we plan to have a special issue of a journal
associated with IWBDA. Details will be posted on the workshop website
when they become available.

KEY DATES:

Call for abstracts published: February 3rd, 2012
Abstract submission deadline: April 2nd, 2012
Abstract acceptance notification: May 7th, 2012
Workshop: June 3rd-4th, 2012

INVITED SPEAKERS:

Jeff Hasty, UC San Diego
Jasmin Fisher, Microsoft, UK
William Shih, Harvard
Milan Stojanovic, Columbia

ORGANIZING COMMITTEE:

Natasa Miskov-Zivanov, University of Pittsburgh (General Chair)
Laura Adam, Virginia Tech (General Secretary)
Xiling Shen, Cornell (Program Committee co-Chair)
Deepak Chandran, University of Washington (Program Committee co-Chair)
Leonidas Bleris, University of Texas at Dallas (Program Committee co-Chair)
Smita Krishnaswamy, Columbia (DAC Liaison)
Chris Myers, University of Utah (Publication Chair)
Jonathan Babb, MIT (Industry/Government Funding Chair)
Aaron Adler, BBN Technologies (Finance co-Chair)
Fusun Yaman, BBN Technologies (Finance co-Chair)

PROGRAM COMMITTEE:

J. Christopher Anderson, UC Berkeley
Adam Arkin, UC Berkeley
Jonathan Babb, MIT
Jacob Beal, BBN Technologies
Leonidas Bleris, UT Dallas
Kevin Clancy, Invitrogen
Douglas Densmore, Boston University
Drew Endy, Stanford
Abhishek Garg, Harvard University
Soha Hassou, Tufts
Mark Horowitz, Stanford
Alfonso Jaramillo, Ecole Polytechnique
Yannis Kaznessis, University of Minnesota
Eric Klavins, University of Washington
Tanja Kortemme, UCSF
Smita Krishnaswamy, Columbia
Natasa Miskov-Zivanov, University of Pittsburgh
Kartik Mohanram, Rice
Chris Myers, University of Utah
Andrew Phillips, Microsoft Research
Mark Riedel, University of Minnesota
Herbert Sauro, University of Washington
Xiling Shen, Cornell
David Thorsley, University of Washington
Christopher Voigt, UCSF
Ron Weiss, MIT
Erik Winfree, Caltech
Chris Winstead, Utah State University

Back to Contents

Call for Tutorials: Midwest Symposium on Circuits and Systems (MWSCAS)

MWSCAS 2012 Call for Tutorials

The IEEE International Midwest Symposium on Circuits and Systems
(MWSCAS) is the oldest Circuits and Systems Symposia sponsored by
IEEE. The 55th edition will be held in Boise, Idaho, USA from August
5-8, 2012. MWSCAS 2012 will include oral and poster sessions, student
paper contest, tutorials given by experts in circuits and systems
topics, and special sessions.

The objective of the MWSCAS 2012 Tutorial Program is offering to
conference attendees an inspiring and informative selection of
tutorials that reflect the state of the art in circuit and system
related research and development.

We encourage to scientific community send submissions of tutorial
proposals on the topics including but not limited to:

- Analog & Mixed-Signal Circuits and Signal Processing
- Digital Circuits and Computer Arithmetic
- Programmable logic, VLSI, CAD and Layout
- Linear and Non-linear Circuits and Systems: Theory and Applications
- Nanoelectronics and Nanotechnology
- Communication and Wireless Systems
- Embedded Electronics
- Image Processing and Multimedia Systems
- RF and Microwave
- Optical and Photonics Systems
- Neural Networks, Neuromorphic Circuits and Fuzzy Systems
- Control Systems, Mechatronics, and Robotics
- Power Electronics and Systems
- Bioengineering Circuits and Systems
- System Architectures
- RFID
- MEMS/NEMS

Each tutorial will consist of a 3 hours session with a 15 minutes
coffee break. The tutorial sessions will be carried out on Sunday,
August 5, 2012.

Tutorial proposals should be submitted in a one-column PDF file to
Tutorial Chair Rubén Alejos-Palomares via email to
ruben.alejos@udlap.mx. Each proposal should include the following
information:

- Title of the tutorial
- Area of the tutorial (refer to the above list of topics)
- Instructor(s) and their credentials (brief bio, including previous
offerings of tutorial, if any)
- Learning objectives
- Target audience and prerequisite knowledge of audience
- 300 Word Abstract (for inclusion in registration materials)
- Keywords
- Full description (1-2 pages to be used for evaluation)

Deadline in order to receive tutorials proposals is March 30th, 2012.

For additional information of MWSCAS 2012, refer to the website
http://www.mwscas2012.org/

Tutorials Co-chairs:

Rubén Alejos-Palomares, Fundación Universidad de las Américas, Puebla,
México. Email: ruben.alejos@udlap.mx
José Luis Vázquez-González, Fundación Universidad de las Américas,
Puebla, México. Email: josel.vazquez@udlap.mx

Back to Contents

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SIGDA E-News 1 March 2012, Vol. 42, No. 03