1 May 2012, Vol. 42, No. 5
Online archive: http://www.sigda.org/newsletter

1. SIGDA News
       From: Srinivas Katkoori <katkoori@cse.usf.edu>
       From: Matthew Guthaus <mrg@soe.ucsc.edu>
2. What is Biological Design Automation?
       Contributing author: Natasa Miskov-Zivanov <nam66@pitt.edu>
       From: Srinivas Katkoori <katkoori@cse.usf.edu>
3. Paper Submission Deadlines
       From: Debjit Sinha <debjitsinha@yahoo.com>
4. Upcoming Conferences and Symposia
       From: Debjit Sinha <debjitsinha@yahoo.com>
5. Upcoming Funding Opportunities
       From: Sudeep Pasricha <sudeep@colostate.edu>
6. Call for Papers: International Conference on Very Large Scale Integration (VLSI-SOC)
       From: Matthew Guthaus <mrg@ucsc.edu>
7. Call for Papers: International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)
       From: Philip Brisk <philip@cs.ucr.edu>
8. Book Review: Introduction to Hardware Security and Trust
       From: Ian G. Harris <harris@ics.uci.edu>
9. Call for Participation: 2012 Young Faculty Workshop at DAC
       From: Soha Hassoun <soha@cs.tufts.edu>

Comments from the Editors

Dear ACM/SIGDA members,

In this issue, we have reprinted a very interesting article on "What
is a Body Sensor network?" If you are interested in contributing to
this column in the future, please contact Srinivas Katkoori
<katkoori@cse.usf.edu>. An article only needs to be about 1 page long
with several references. All articles are included in the ACM digital
library and there is no restriction for the reproduction of the
article for printed publication later.

Matthew Guthaus, E-Newsletter Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Sudeep Pasricha, E-Newsletter Associate Editor;
Srinivas Katkoori, E-Newsletter Associate Editor

Back to Contents

SIGDA News

"EDA grew 16% in 2011, EDAC says"
http://www.eetimes.com/electronics-news/4370602/EDA-grew-16--in-2011--EDAC-says
EDA and IP vendors posted another strong quarter of sales in the
fourth quarter of 2011, turning in revenue of $1.7 billion, up 10
percent compared to the third quarter and up 12.8 percent compared to
the fourth quarter of 2010, according to the EDA Consortium EDAC)'s
market statistics service. For the full year 2011, EDA and IP sales
totaled $6.13 billion in 2011, up 16 percent from $5.28 billion in
2010, according to EDAC.

"ISPD: Semiconductors aim for 8-nm node"
http://www.eetimes.com/electronics-news/4370573/ISPD--Semiconductors-aim-for-8-n...
The possible pathways down to the 8-nanometer semiconductor
fabrication node were detailed last week at the ACM International
Symposium on Physical Design (ISPD) in Napa, Calif., albeit through a
glass darkly. What's for sure is that the pathway is fraught with
engineering peril as three competing technologies tool up for mass
production capabilities. However, keynote speaker Burn Lin, a TSMC
distinguished Fellow, claimed that one of three alternatives was sure
to surmount the downward scaling hurdles to 8-nm design rules.

"Researchers prototype implantable microphone for deaf"
http://www.eetimes.com/electronics-news/4371946/Researchers-prototype-implantabl...
A proof-of-concept prototype microphone implanted in the middle ear
promises to partly offset the need for wearing an outer hearing aid.
The device would still require patients to wear a charger behind the
ear while sleeping to recharge an implanted battery. The current
prototype of the packaged, middle-ear microphone measures 2.5 x 6.2 mm
and weighs 25 mgrams, or less than a thousandth of an ounce.

"Smart memory seen as cure for user-interface bottlenecks"
http://www.eetimes.com/electronics-news/4371980/Smart-memory-seen-as-cure-for-us...
Next-generation augmented reality displays will employ
smart-recognition of their users that melds context-sensitive
voice-and-gesture commands with total-surrounding awareness of other
people, places and things, according to John Kispert, CEO of Spansion
Inc., who gave the keynote address at the Globalpress Electronics
Summit 2012 last week. But smart memory will be needed to wean these
advanced user-interfaces off cloud connectivity dependence, Kispert
said.

"Chip execs see 20 nm variants, 3-D ICs ahead"
http://www.eetimes.com/electronics-news/4371833/Chip-execs-see-20-nm-variants--3...
Next-generation 20 nm processes can support optimized versions for low
power and high performance, according to an IBM
expert. GlobalFoundries will decide in August whether or not it will
offer such variations.

"STC receives 'trusted foundry' label from DoD"
http://www.eetimes.com/electronics-news/4371810/STC-receives--trusted-foundry--l...
The College of Nanoscale Science and Engineering's Smart System
Technology and Commercialization Center of Excellence (STC) in
Canandaigua, NY has been designated as a Trusted Foundry by the
U.S. Department of Defense's Defense Microelectronics Agency.

"GlobalFoundries installs gear for 20-nm TSVs"
http://www.eetimes.com/electronics-news/4371752/GlobalFoundries-installs-gear-fo...
GlobalFoundries is installing equipment to make through-silicon vias
in its Fab 8 in New York. If all goes well, the company hopes to take
production orders in the second half of 2013 for 3-D chip stacks using
20 and 28 nm process technology. GlobalFoundries is working with
multiple packaging companies including Amkor to develop process flows
to create stacks with through-silicon vias (TSVs). The foundry’s
archrival, Taiwan Semiconductor Manufacturing Co., announced late last
year it will go it alone, handling all steps in the 3-D stacking
process in a move TSMC said will reduce costs and risks of shipping
the thin wafers the technique requires.

"Nvidia, BGI partner on cloud DNA sequencing service"
http://www.eetimes.com/electronics-news/4371751/Nvidia--BGI-partner-on-cloud-DNA...
BGI, the world’s largest genomics institute announced on Wednesday (25
April 2012) it would launch a new cloud-based service for researchers
to do next-generation sequencing (NGS) bioinformatics analysis cheaply
within the cloud. The new cloud-based DNA sequencing service, dubbed
“EasyGenomics,” uses a hybrid computing system featuring both CPUs and
Nvidia GPUs for added acceleration, which the firm claims can cut the
analysis of DNA big data from days to hours compared with CPU-only
based systems.

"Mentor's next-gen emulator promises more performance, capacity"
http://www.eetimes.com/electronics-news/4371660/Mentor-s-next-gen-emulator-promi...
EDA vendor Mentor Graphics Corp. Wednesday (April 25) announced the
availability of its next-generation hardware emulation system,
Veloce2, promising twice the performance, twice the capacity and four
times productivity gain in the same footprint and power consumption as
its predecessor.

"Intel launches Ivy Bridge processor"
http://www.eetimes.com/electronics-news/4371471/Intel-launches-Ivy-Bridge-proces...
Intel is formally launching its Ivy Bridge processor to the market on
23 April 2012. Ivy Bridge is the first device to be realeased
officially on the company's 22-nm manufacturing process technology
which includes FinFETs, which are transistors built into a vertical
fin of silicon.

"Report: Semiconductor IP market to double in five years"
http://www.eetimes.com/electronics-news/4370382/http-www-marketsandmarkets-com-M...
The semiconductor intellectual property (IP) market is forecast to
grow from $2.5 billion in 2012 to $5.7 billion in 2017, a compound
annual growth rate of more than 14 percent, according to a market
research report by MarketsandMarkets, a market research and consulting
company based in the U.S.

"Trash-powered cloud: Apple taps landfill biogas for data center"
http://news.cnet.com/8301-11386_3-57425095-76/trash-powered-cloud-apple-taps-lan...
Apple discloses that the fuel cells at its North Carolina data center
will run on biogas captured from landfills, part of its plan to
operate using 60 percent on-site renewable energy.

"Here comes silicene, possible graphene replacement"
http://www.edn.com/article/521635-Here_comes_silicene_possible_graphene_replacem...
Science researchers have reported the growth of a single layer of
silicon on top of silver, in a hexagonal 2-D form of silicon similar
to the graphene form of carbon.

Back to Contents

What is Biological Design Automation?

Natasa Miskov-Zivanov, University of Pittsburgh

Biological systems are astoundingly complex and it is often hard
(if not impossible) to comprehend all their details. Despite their
complexity, there has been an unceasing attempt to understand and
control them. As described in [1], evolution has driven towards
recurrent molecular "designs" and circuit motifs, and it is
"increasingly clear that there are principles of organization,
architecture, and (evolutionary) design in biological circuits,
but there are many details and deep principles yet to be discovered."

At the same time, in electronic circuit design, circuits are designed
by selecting and combining well understood electronic components
for the purpose of implementing the desired functionality. Electronic
design automation (EDA) allows for the efficiency of this process
by abstracting away details and using higher level building blocks
to describe computational systems. Nevertheless, EDA applies
automation to the design of systems that are amenable to our logic
and intuition. These systems are modular, hierarchically organized,
and their behavior is controllable and predictable.

Circuit designers are increasingly more drawn to Biology: as they
manage to design complex systems, why not study complex biological
systems, design and control them in the same manner? As a response
to this, biologists often raise another question: is the complexity
of systems that engineers are designing comparable to the complexity
of biological systems?

To this end, role of EDA, design automation techniques and tools,
can be probed from the perspective of three emerging fields of Biology
(and engineering, as well): Systems Biology, Synthetic Biology
and Bio-Inspired Computing.

Systems Biology is an approach to biological research that focuses
on the interactions between components of a biological system and
how those interactions give rise to the dynamic behavior of the
system, in contrast to the more traditional molecular biologists’
reductionist approach. Alon starts the description of the cell in
his textbook on Systems Biology [2] as "an integrated device made
of several thousand types of interacting proteins." Systems biologists
analyze molecular systems such as genetic regulatory networks,
metabolic networks, and protein networks. Given the vast experience
in reasoning about complex circuits and systems, engineers are uniquely
equipped to assist with development of tools for the modeling and
analysis of such systems [1]. McAdams and Shapiro [3] have shown
in nineties that viewing a genetic circuit as an electronic circuit
can yield new insights and open up the application of engineering
tools to genetic circuits. Several approaches have been proposed
for developing abstraction and analysis methods for these circuits.
In early sixties, Kauffman suggested using random Boolean networks
as suitable models of biological networks [4]. Continuing with similar
arguments in [5], Thomas details different levels at which biological
systems are often described (verbal, logical and differential).
He describes a sigmoidal response often seen in biological interactions,
and emphasizes the importance of logical (step function) for capturing
dynamical, qualitative behavior of these systems. Starting from
these seminal works, logical modeling has been applied to a number
of biological networks [6,7,8]. Once designed, these logical models,
or circuits, are simulated in a synchronous, asynchronous, or
combined manner. Given the complexity of biological networks,
such logic circuit-based approach allows for capturing larger,
more coarse-grained networks and thus, represents means for proving
our hypotheses about the interactions of components and network
responses to stimulations. While most of the circuit-inspired
models developed thus far are simple, existing tools still require
considerable time to exhaustively analyze system response and its
robustness under different scenarios. Recently, several EDA methods
that utilize symbolic modeling, verification techniques and hardware
emulation have been suggested to improve the efficiency of these
studies [6,7,8].

In recent years, biologists and engineers have also been working
together towards creating central concepts of Synthetic Biology:
rational design of synthetic gene circuits by means of modularized,
standard parts. Such synthetic genetic circuits should, for example,
enable bacteria to consume toxic waste, destroy tumors, and produce
drugs and bio-fuels. Synthetic Biology field aims at adapting methods
and ideas from circuit design to biology (e.g., part composability,
abstraction hierarchy). Several computational tools embracing these
concepts have been developed [9]. However, the design of biological
circuits that are able to reproduce a desired function is a hard
task and its automation still represents a major challenge. As EDA
enables the design of more complex integrated circuits each year,
experiences from EDA field could be applied to the development of
biological design automation. Recently, there has been some progress
towards meeting this goal by developing standards, abstractions,
and automated construction of synthetic genetic circuits. The Registry
of Standard Biological Parts [10] has been established to provide
a collection of genetic parts that can be mixed and matched to build
synthetic biology devices and systems. A list of computational tools
has also been created in a similar attempt to maintain a list of tool
standards and specifications in synthetic biology [11]. These tools
can be used to analyze, combine and visualize components. However,
obtaining more efficient and accurate methods for modeling, analysis,
and design in synthetic biology still remains a challenge [12].

Despite the continuing advances in circuit design, state-of-the-art
in Systems and Synthetic Biology attests that we are still very much
dazzled by the complexity of the world around us. At the same time,
computing has been inspired by nature from its beginnings: Alan Turing
asked whether computers could think like humans and John von Neumann
sketched out an automaton that could self-replicate [13]. Even then,
it was questioned whether to continue creating faster, more efficient
algorithms and hardware that exhibit centralized control or to place
more emphasis on robustness, adaptability, and self-assembly arising
from the interactions of many components. These latter approaches are
today known as yet another field that brings together computing and
biology - biologically inspired computing - linking disciplines such
as artificial intelligence, evolutionary computation, biorobotics,
artificial life, and agent-based systems [13].

To summarize, biological design automation is a new field that could
largely benefit from EDA practices. Engineers have been designing tools,
devices and gadgets to assist us in our everyday matters and often
help us overcome obstacles that nature poses. With this novel wave of
research, engineers are reaching closer to nature itself: they are
assisting biologists in studying nature, as well as using its principles,
combined with EDA practices, to design novel systems with a wide range
of applications, from medicines to fuels to bio-inspired circuits.
Some progress has been made in this endeavor; many advances are yet
to come. Spice up EDA with randomness, unpredictability and even more
complexity, and the outcome is full of exciting challenges for a
rising generation of Bio-CAD engineers.

References

[1] C. J. Myers, "Engineering genetic circuits," Chapman & Hall/CRC, 2010.

[2] U. Alon, "An introduction to Systems Biology: Design Principles
of Biological Circuits," Chapman & Hall/CRC, 2006.

[3] H. H. McAdams and L. Shapiro, "Circuit simulation of genetic networks,"
Science, Vol. 269, pp. 650-656, 1995.

[4] S. A. Kauffman, "Metabolic stability and epigenesis in randomly
constructed genetic nets," Journal of Theoretical Biology, Vol. 22,
pp. 437-467, 1969.

[5] R. Thomas and R. D'Ari, "Biological Feedback," CRC Press, 1990.

[6] N. Miskov-Zivanov, A. Bresticker, S. Venkatakrishnan, P. Kashinkunti,
D. Krishnaswamy, D. Marculescu and J. R. Faeder, "Regulatory Network
Analysis Acceleration with Reconfigurable Hardware," International
Conference of the IEEE Engineering in Medicine and Biology Society
(EMBC), 2011.

[7] J. Fisher and N. Piterman, "The executable pathway to biological
networks," Briefings in Functional Genomics, Vol. 9, pp. 79-92, 2010.

[8] A. Garg, A. Di Cara, I. Xenarios, L. Mendoza, and G. De Micheli,
"Synchronous versus asynchronous modeling of gene regulatory networks,"
Bioinformatics Vol. 24, pp. 1917–1925, 2008.

[9] M. A. Marchisio and J. Stelling, "Computational design tools for
synthetic biology," Current Opinion in Biotechnology, Vol. 20,
pp. 479-485, 2009.

[10] Registry of Standard Biological Parts,
http://partsregistry.org/Main_Page.

[11] Computational Tools for Synthetic Biology,
http://openwetware.org/wiki/Computational_Tools .

[12] P. E. M. Purnick and R. Weiss, " The second wave of synthetic
biology: from modules to systems," Nature Reviews Molecular Cell
Biology Vol. 10, pp. 410-422, 2009.

[13] J. Bongard, “Biologically Inspired Computing,” IEEE Computer,
pp. 95-98, 2009.

Back to Contents

Paper Submission Deadlines

VLSI-SoC’12 – Int’l Conference on Very Large Scale Integration and System on Chip
Santa Cruz, CA
Deadline: May 3, 2012
Oct 7-12, 2012
http://vlsisoc2012.soe.ucsc.edu/

HiPC'12 - Int'l Conference on High Performance Computing
Pune, India
Deadline: May 16, 2012
Dec 18-21, 2012
http://www.hipc.org/

MICRO'12 - Int'l Symposium on Microarchitecture
Vancouver, Canada
Deadline: Jun 8, 2012 (Abstracts due: Jun 1, 2012)
Dec 1-5, 2012
http://www.microarch.org/micro45/

ICFPT'12 - Int'l Conference on Field-Programmable Technology
Seoul, Korea
Deadline: Jun 8, 2012
Dec 10-12, 2012
http://www.icfpt.org/

ICPADS'12 - Int'l Conference on Parallel and Distributed Systems
Singapore, Singapore
Deadline: Jun 15, 2012
Dec 17-19, 2012
http://pdcc.ntu.edu.sg/icpads2012/

HLDVT’12 – Int’l High-Level Design, Validation and Test Workshop
Huntington Beach, CA
Deadline: Jun 17, 2012
Nov 9-10, 2012
http://www.hldvt.com/12/

ISED’12 – Int’l Symposium on Electronic System Design
Kolkata, India
Deadline: Jun 17, 2012
Dec 19-22, 2012
http://ised.seedsnet.org/

HiPEAC'13: Int'l Conference on High Performance Embedded Architectures & Compilers
Berlin, Germany
Deadline: Jun 18, 2012
Jan 21-23, 2013
http://www.hipeac.net/ hipeac2013

BIOCAS'12 - Biomedical Circuits and Systems Conference
Hsinchu, Taiwan
Deadline: Jun 30, 2012
Nov 28-30, 2012
http://www.biocas2012.org/

ASP-DAC'13 - Asia and South Pacific Design Automation Conference
Yokohama, Japan
Deadline: Jul 13, 2012
Jan 22-25, 2013
www.aspdac.com/aspdac2013/

ISSCC'13 - Int'l Solid-State Circuits Conference
San Francisco, CA
Deadline: Sep 10, 2012
Feb 17-21, 2012
http://isscc.org/

Back to Contents

Upcoming Conferences and Symposia

ASYNC'12 – Int’l Symposium on Asynchronous Circuits and Systems
(co-located with NOCS’12)
Copenhagen, Denmark
May 7-9, 2012
http://asyncsymposium.org

NOCS'12 – Int’l Symposium on Networks-on-Chip
(co-located with ASYNC’12)
Copenhagen, Denmark
May 9-11, 2012
http://www2.imm.dtu.dk/projects/nocs_2012/nocs/Home.html

EWME'12 – European Workshop on Microelectronics Education
Grenoble, France
May 9-11, 2012
http://cmp.imag.fr/conferences/ewme2012

BSN’12 – Int’l Conference on Wearable and Implantable Body Sensor Networks
London, UK
May 10-12, 2012
http://www.bsn2012.org

ISCAS'12 - Int'l Symposium on Circuits and Systems
COEX, Seoul, Korea
May 20-23, 2012
http://iscas2012.org/

DAC’12 – Design Automation Conference
San Fransisco, CA
Jun 3-7, 2012
http://www2.dac.com/

SLIP’12 - System Level Interconnect Prediction
(co-located with DAC’12)
San Francisco, CA
June 3, 2012
http://www.sliponline.org

DFM&Y'12 - Int'l Workshop on Design for Manufacturability & Yield
San Francisco, CA (Co-located with DAC’12)
Jun 4, 2012
http://vlsicad.ucsd.edu/DFMY

IWBDA'12 - Int'l Workshop on Bio-Design Automation
San Francisco, CA (Co-located with DAC’12)
Jun 4-5, 2012
http://iwbda2012.csb.pitt.edu

ISCA’11 – Int’l Symposium Computer Architecture
Portland, OR
Jun 9-13, 2012
http://isca2012.ittc.ku.edu/

AHS’12 - NASA/ESA Conference on Adaptive Hardware and Systems
Nuremburg, Germany
Jun 25-28, 2012
http://www.see.ed.ac.uk/ahs2012/

ASQED'12 - Asia Symposium on Quality Electronic Design
Kuala Lumpur, Malaysia
Jul 10-12, 2012
http://www.asqed.org/

MEMOCODE'12 – Int’l Conference on Formal Methods and Models for Codesign
Arlington, VA
Jul 16-18, 2012
http://www.memocode-conference.com

PACT'12 - Int'l Conference on Parallel Architectures and Compilation
Techniques
Minneapolis, MN
Sep 21-25, 2012
http://www.pactconf.org

BodyNets'12 – Int’l Conference on Body Area Networks
Oslo, Norway
Sep 24-26, 2012
http://www.bodynets.org

VLSI-SoC’12 – Int’l Conference on Very Large Scale Integration and System on Chip
Santa Cruz, CA
Oct 7-12, 2012
http://vlsisoc2012.soe.ucsc.edu/

ESWEEK'12 - Embedded Systems Week (CASES, CODES+ISSS, and EMSOFT)
Tampere, Finland
Oct 7-12, 2012
http://www.esweek.org

Wireless Health’12
San Diego, CA
Oct 22-25, 2012
http://www.wirelesshealth2012.org/

ICCAD’12 – Int’l Conference on Computer-Aided Design
San Jose, CA
Nov 5-8 2012
http://www.iccad.com

Back to Contents

Upcoming Funding Opportunities

ASEE

Office of Naval Research (ONR) Sabbatical Leave Program
Deadline: N/A
http://onr.asee.org/

Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Deadline: Continuous
http://www.asee.org/fellowships/nrl/about.cfm

DARPA

Microsystems Technology Office-Wide Broad Agency - DARPA-BAA-10-35
Deadline: September 1, 2012
https://www.fbo.gov/spg/ODA/DARPA/CMO/DARPA-BAA-10-35/listing.html

DOD

Robust Computational Intelligence - AFOSR-BAA-2011-01
Deadline: Continuous
http://www.grants.gov/search/search.do?oppId=88213&mode=VIEW

Systems and Software - AFOSR-BAA-2011-01
Deadline: Continuous
http://www.grants.gov/search/search.do?oppId=88213&mode=VIEW

ERDC BAA - Computational Science and Engineering (ITL-1)
Deadline: Continuous
http://www.mvk.usace.army.mil/contract/docs/BAA.pdf

Advanced Distributed Sensor Technologies - BAA 57-09-06
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm

Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm

High Performance Computing on Massively Parallel Architectures (BAA 64-09-01)
Deadline: Continuous
http://heron.nrl.navy.mil/contracts/baa/index.htm

ASEE-NRL Postdoctoral Fellowship Program
Deadline: N/A
http://hroffice.nrl.navy.mil/jobs/postdoc.htm

DOE

Postdoctoral Appointments
Deadline: N/A
http://www.sandia.gov/careers/postdoc.html

Sabbaticals and Faculty Appointments
Deadline: continuous
http://www.nrel.gov/rpp/sabbaticals.html

McDonnell Foundation

Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Deadline: continuous
http://www.jsmf.org/programs/cs/

NSF

Integrative Graduate Education and Research Traineeship Program (IGERT)
Letter of Intent: May 1, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf11533

Cyberlearning: Transforming Education (Cyberlearning)
Letter of Intent: May 14, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf11587

Partnerships for International Research and Education (PIRE)
Deadline: May 15, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf11564

Core Techniques and Technologies for Advancing Big Data Science & Engineering (BIGDATA)
Deadline: June 13, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf12499

Research Coordination Networks
Deadline: June 15, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf11531

Industry/University Cooperative Research Centers Program (I/UCRC)
Deadline: June 29, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf12516

Cyberlearning: Transforming Education (Cyberlearning)
Deadline: July 16, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf11587

Faculty Early Career Development (CAREER) Program
Deadline: July 23-25, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf11690

Failure-resistant systems (FRS)
Deadline: July 26, 2012
http://www.nsf.gov/publications/pub_summ.jsp?org=NSF&ods_key=nsf12556

SRC

Call for Grant Applications in Cross-disciplinary Semiconductor Research (CSR)
Deadline: June 4, 2012
http://www.src.org/compete/s201212/

Focus Center Research Program
Deadline (White Paper): June 15, 2012
http://www.src.org/compete/s201209/

Back to Contents

Call for Papers: International Conference on Very Large Scale Integration (VLSI-SOC)

20th IFIP/IEEE International Conference on Very Large Scale Integration
VLSI-SoC 2012
October 7-10, 2012
Santa Cruz, CA, USA
Dream Inn Hotel

http://www.vlsi-soc.com

VLSI-SoC 2012 is the 20th in a series of international conferences
sponsored by IFIP TC 10 Working Group 10.5, IEEE CEDA and IEEE CASS
that explores the state-of-the-art and the new developments in the
field of Very Large Scale Integration (VLSI) and System-on-Chip
(SoC). Previous Conferences have taken place in Edinburgh, Trondheim,
Tokyo, Vancouver, Munich, Grenoble, Gramado, Lisbon, Montpellier,
Darmstadt, Perth, Nice, Atlanta, Rhodes, Florianopolis, Madrid and
Hong Kong. The purpose of VLSI-SoC is to provide a forum to exchange
ideas, and show academia/industrial research results in the fields of
VLSI/ULSI Systems, SoC design, VLSI CAD and Microelectronic Design and
Test.

Topics of interest include but are not limited to:
* Analog and Mixed-Signal IC Design
* Circuits and Systems for Micro-sensing Applications
* 3-D Integration, Physical Design, Compact Modeling, and
Electromagnetic Analysis
* Design for Variability, Reliability, Fault Tolerance, Test
* Digital Signal Processing and Image Processing IC Design
* New Devices, MEMS and Microsystems
* Prototyping, Validation, Verification, Modeling and Simulation
* System-On-Chip Design, Digital Architectures
* Embedded Systems Design and Real-Time Systems
* Reconfigurable Systems, Compiler
* Logic and High-Level Synthesis
* Low-Power and Thermal-aware Design

PAPER SUBMISSION

Papers should present original research results not published or
submitted for publication in other forums. Electronic submission in
PDF format to the http://www.vlsi-soc.com web site is required. The
proceedings will be published by IEEE and available through IEEE
Xplore. They will be distributed during the conference to all
participants. A selection of the conference best papers will be
invited to submit an extended version to be included as chapters of a
book to be published by Springer.

Paper Submission Deadline: May 3, 2012 11:59pm PDT **FIRM**
Special Session Papers: May 3, 2012 11:59pm PDT **FIRM**
Notification of acceptance: June 30, 2012
Camera-ready: July 11, 2012

PAPER FORMAT

Papers should not exceed 6 pages (single-spaced, 2 columns, 10pt
font). Submissions should be in camera-ready, following the IEEE
proceedings specifications located at:
http://www.ieee.org/web/publications/pubservices/confpub/AuthorTools/conferenceT...

PAPER PUBLICATION AND PRESENTER REGISTRATION

Papers will be accepted for regular or poster presentation at the
conference. Every accepted paper MUST have at least one author
registered to the conference by the time the camera-ready paper is
submitted; the author is also expected to attend the conference and
present the paper. A limited number of travel grants are available to
needy PhD students. Please see the web site for more information.

PHD FORUM

The VLSI-SoC 2012's Ph.D. Forum is a poster session dedicated to the
exchange of ideas and experiences of Ph.D. students from different
parts of the world. Elected Ph.D. students have an opportunity to
discuss their thesis and research work with specialists within the
system and design automation communities. This exchange offers a good
opportunity for students to receive valuable feedback and gain
exposure in the job market. Furthermore, this forum also provides a
great chance for industry officials to meet junior researchers, giving
an avenue for incorporating the latest research developments into
their companies. More information in the conference web page.

SPECIAL SESSIONS

1) Memristive Computing
Organizer: Sung-Mo (Steve) Kang, UC Santa Cruz, USA

Memristors and memristive devices have been recently realized in
nanoscale. Several recent implementations have brought forth the
potential for revolutions in non-volatile storage and reconfigurable
computing. This special session is specifically focused at using
memristive devices for computing in programmable systems such as
FPGAs.

2) Open Source Tools and Methodologies for Research
Organizer: Jose Renau, UC Santa Cruz, USA

Open source tools enable both academia and industry to research,
develop, and share common platforms in complex research
tasks. However, most often these open source tools and methodologies
are unsung and, in fact, difficult to publish. This special session is
specifically focused at recognizing the most important and useful open
source tools and methodologies that aid research.

Special session papers should present original material not published
or submitted for publication in other forums. These papers will
undergo normal peer review. Electronic submission in PDF format to the
http://www.vlsi-soc.com web site is required.

ORGANIZING COMMITTEE:

General Chair:
Matthew Guthaus, UC Santa Cruz, USA

Program Chairs:
Ayse Coskun, Boston Univ., USA;
Andreas Burg, EPFL, Switzerland

Special Sessions Chair:
Sung-Mo "Steve" Kang, UC Santa Cruz, USA
Jose Renau, UC Santa Cruz, USA

Local Arrangement Chair:
Jose Renau, UC Santa Cruz, USA

Publication Chairs:
Srinivas Katkoori, Univ of South Florida, USA;
Ricardo Reis, UFRGS, Brazil

Publicity Chair:
Ricardo Reis, UFRGS, Brazil

Registration Chair:
Rajsaktish Sankaranarayanan, UC Santa Cruz, USA

Finance Chair:
Baris Taskin, Drexel, USA

PhD Forum Chair:
Ken Pedrotti, UC Santa Cruz, USA

Steering Committee:
Manfred Glesner, TU Darmstadt, Germany;
Salvador Mir, TIMA, France;
Ricardo Reis, UFRGS, Brazil;
Michel Robert, U. Montpellier, France;
Luis Miguel Silveira, INESC ID, Portugal

SPONSORS

IFIP WG 10.5
IEEE CEDA
IEEE Circuits and Systems Society
ACM SIGDA
UC Santa Cruz
CITRIS

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Call for Papers: International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)

CALL FOR PAPERS

HiPEAC 2013: 8th International Conference on High-Performance and
Embedded Architectures and Compilers

January 21-23, 2013, Berlin, GERMANY

http://www.hipeac.net/hipeac2013

IMPORTANT DATES:
* Workshops/tutorials: June 1, 2012
* Papers: June 18, 2012
* Paper selection: November 15, 2012
* Posters: October 15, 2012

The HiPEAC conference is the premier scientific networking forum for
experts in computer architecture, programming models, compilers and
operating systems for embedded and general-purpose systems. Emphasis
is given on cross-cutting research and innovative ideas (new
programming models, novel architecture approaches, new technologies,
etc.). The conference hosts a number of associated workshops,
tutorials, a large poster session and an exhibition that run in
parallel with the conference. The 8th HiPEAC conference will take
place in Berlin, Germany from Monday 21 to Wednesday January 23, 2013.

JOURNAL FIRST PUBLICATION MODEL

In 2011, TACO and HiPEAC jointly carried out an experiment with a
publication model where original contributions on HiPEAC topics were
solicited for TACO. Record-high numbers of submitted and accepted
papers witness the significant interest in this model. This year, TACO
seeks original submissions at any time. Accepted TACO papers by
November 15, 2012 and whose topics match those of HiPEAC will be
selected and invited for presentation at HiPEAC conference. In order
to enjoy two rounds of review, and to be considered for invitation to
present at the HiPEAC 2013 conference, papers should be submitted no
later than June 18, 2012. Accepted papers will be published in
regular issues of ACM TACO.

For submission details, please refer to
http://mc.manuscriptcentral.com/taco.

Topics of interest to HiPEAC 2013 include, but are not limited to:

- Processor architectures
- Memory system optimization
- Power, performance and implementation efficient designs
- Reliability and real-time support in processors, compilers and
run-time systems
- Network and security processors
- Application-specific processors and accelerators
- Reconfigurable architectures
- Simulation and methodology
- Hardware and run-time support for programming languages
- Compiler techniques
- Feedback-directed optimization
- Program characterization and analysis techniques
- Dynamic compilation, adaptive execution, and continuous
profiling/optimization
- Binary translation/optimization
- Code size/memory footprint optimizations

ORGANIZING COMMITTEE

HiPEAC 2013 General Chairs:
* Ben Juurlink (Technische Universität Berlin, Germany)
* Keshav Pingali (University of Texas Austin, USA)

Program Chairs:
* André Seznec (INRIA/IRISA, France)
* Lawrence Rauchwerger (Texas A&M University, USA)

Editor-in-chief of ACM Transactions on Architecture and Code Optimization:
* Tom Conte (Georgia Institute of Technology, USA)

Poster Chairs:
* Koen De Bosschere (Ghent University, Belgium)
* Qing Yi (University of San Antonio, USA)

Workshops/Tutorials Chair:
* Sascha Uhrig (Technische Universität Dortmund, Germany)

Industrial exhibit and European projects sub-committee:
* Henri-Pierre Charles (French Alternative Energies and Atomic Energy
Commission, France)
* Rosa M. Badia (Barcelona Supercomputing Center, Spain)

Publicity Chairs:
* Philip Brisk (U.C Riverside, USA)
* Nikola Puzovic (Barcelona Supercomputing Center, Spain)

Finance Chair:
* Jeroen Borghs (Ghent University, Belgium)

Submission Chair:
* Michiel Ronsse (Ghent University, Belgium)

Web and Registrations Chair:
* Klaas Millet (Ghent University, Belgium)

Local organizing committee:
* Nico Moser (Technische Universität Berlin, Germany)
* Paula Herber (Technische Universität Berlin, Germany)
* Reinier van Kampenhout (Fraunhofer FIRST, Germany)

Steering Committee:
* Anant Agarwal (MIT, USA)
* Koen De Bosschere (Ghent University, Belgium)
* Albert Cohen (INRIA, France)
* Tom Conte (Georgia Institute of Technology, USA)
* Wen-mei W. Hwu (UIUC, USA)
* Walid Najjar (UC Riverside, USA)
* Per Stenstrom (Chalmers University, Sweden, Chair)
* Theo Ungerer (University of Augsburg, Germany)
* Mateo Valero (UPC, Spain)

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Book Review: Introduction to Hardware Security and Trust

Introduction to Hardware Security and Trust
by editors Mohammad Tehranipoor and Cliff Wang
(Springer, 2012, ISBN 978-1-4419-8080-9, 427 pp., $179)

Review by:

Ian G. Harris, Associate Professor
Department of Computer Science
University of California Irvine

Cybersecurity is clearly an important topic of research today and
there is a large community of researchers addressing problems in that
space. Traditional computer security research has primarily focused on
software artifacts, but recently there has been a significant increase
in research on the security of hardware components. As embedded
devices are more fully integrated into society, it has become clear
that hardware vulnerabilities can be exploited by attackers, and that
hardware strengths can be used by designers to support
security. Introduction to Hardware Security and Trust by editors
Mohammad Tehranipoor and Cliff Wang (Springer, 2012, ISBN
978-1-4419-8080-9, 427 pp., $179), presents an outline of research in
hardware security, summarizing research efforts on virtually all
research problems in the field.

The field of hardware security and trust is closely related to VLSI
testing research. Testing is needed to discover modifications made by
an attacker who has altered the design in a permanent or transient
way. Possessing a knowledge of testing is also important to understand
the perspective of the attacker, who may employ testing techniques to
reverse engineer the design or extract confidential data. The book
provides essential testing background in the first chapter, preparing
the reader for the test issues which arise in future chapters.

Chapters 2 and 3 describe the use of dedicated hardware to perform
encryption. Research in hardware encryption engines has a long history
and these two chapters do a good job of presenting current work in the
field. Encryption engines are key components of any system security
measure, either in hardware or software, and hardware implementations
are efficient. Hardware implementations of several hashing functions
are described in Chapter 2, and Chapter 3 describes the hardware
implementation of the RSA encryption algorithm. My only wish for this
section is that the implementation of other encryption algorithms, in
addition to RSA, could have been included.

The next three chapters describe techniques to identify and protect
proprietary design information. Chapter 4 provides a survey on
Physically Unclonable Functions (PUFs), classifying the different PUFs
which have been developed and describing their implementations in
detail. A survey on hardware metering, protecting a design from
overbuilding at the foundry, is presented in Chapter 5. Hardware
metering approaches produce subtly different integrated circuits (ICs)
using a single mask set by incorporating some programmability which
can be altered post-production to activate the IC. Digital
watermarking, described in Chapter 6, prevents IP theft by introducing
uniquely-identifiable changes into the design which do not affect
functionality.

Hardware security techniques must defend against attackers who have
direct access to the hardware and have the sophistication to test and
possibly dismantle the IC. Chapter 7 discusses physical attacks and
the incorporation of tamper resistance to protect against
them. Non-invasive physical attacks use IC testing techniques to
identify information leakage through side channels such as
power/performance variation and photon emission. IC side channel
attacks and their countermeasures are detailed in Chapter 8, and
embedded microprocessor side channels are discussed in Chapter 11.

If an attacker modifies a design before fabrication, the design may
include a “hardware trojan” which causes the IC to exhibit malicious
behavior under predetermined conditions. Chapter 14 provides a
taxonomy of the different types of hardware trojans and the impact
that each class can have on the IC’s behavior. Chapter 15 classifies
the different testing approaches which have been proposed to detect
hardware trojans. Chapter 16 continues by presenting design techniques
which facilitate the detection of hardware trojans, adding hardware
support to sense variations created by trojans. Chapter 16 also
describes the use of proof-carrying hardware descriptions to formally
verify that a design is trojan-free.

A common attack goal is to retrieve confidential information from
internal IC components. Abuse of on-chip test circuitry by an attacker
can provide direct access to internal signals and storage
elements. Chapters 17 and 18 review the vulnerabilities inherent in
scan chain design, and suggest alternative, secure scan chain
implementations. Several chapters focus on the unique security
properties of different classes of circuits. Chapter 9 discusses Field
Programmable Gate Arrays (FPGAs) whose design configurations are
stored in on-chip memories and are vulnerable to theft and
manipulation. Chapter 12 describes the range of attacks on Radio
Frequency IDentification (RFID) tags, both active and passive. Chapter
13 surveys memory encryption techniques to support memory integrity
protection.

The title of this book is accurate; it provides an introduction to
research in the field of hardware security and trust. This book will
serve as an excellent primer for anyone starting to perform research
in the field, and a reference for those already working on these
problems. Designers and researchers who are interested in hardware
security will find this book to be a valuable resource.

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Call for Participation: 2012 Young Faculty Workshop at DAC

The 2012 Young Faculty workshop at DAC will be held on Sunday, June 3,
2012, 8:45am to 5:30 pm.

This is a special workshop organized for new, or soon to be, faculty
in the fields of electronic design automation (EDA) and Embedded
Systems and Software (ESS). The workshop will be organized as
presentations by senior professionals, with additional opportunities
to network with some of the established researchers and funding
officers from NSF, SRC, and industry. The themes covered include:
Getting an Academic Job, Research - papers, conferences and proposals
(including NSF CAREER proposals) , Teaching - Best practices and
example courses, and a “Speed Networking” event.

Who can participate?
- first or second year faculty who would benefit from networking and
some early career advice.
- Graduating PhD students interested in an academic job: (nth year,
and n-1 year)
- Post docs
- industry folks interested in an academic position

This event is sponsored by DAC, SIGDA, CEDA, SRC, and NSF. The
sponsorship funds will enable us to cover some travel and
accommodations.

To apply: DEADLINE EXTENDED TILL MAY 2nd

Visit here to complete the application (even if you are not applying
for a travel grant):
https://sites.google.com/site/dacyfws/home/application-form

Visit here to register for the workshop through the DAC registration process:
http://www.dac.com/dac+2012+registration.aspx

More detailed information is available at:
http://www.dac.com/App_Content/files/49/Young_Faculty_120326.pdf

If you have any questions, do not hesitate to contact the organizers!

Organizers:

Steven Levitan <levitan@pitt.edu> - Univ. of Pittsburgh, PA
Soha Hassoun <soha@cs.tufts.edu> - Tufts Univ., Medford, MA
Kartik Mohanram <kmram@pitt.edu> - Univ. of Pittsburgh, PA

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