SIGDA E-News 1 July 2012, Vol. 42, No. 7

1 July 2012 :: ACM/SIGDA E-NEWSLETTER :: Vol. 42, No. 7
 Special Interest Group on Design Automation
1 July 2012, Vol. 42, No. 7
Online archive:
1. SIGDA News
    From: Sudeep Pasricha <>
    From: Lin Yuan <>

2. What is an Organic FET?
    Contributing authors:
    Arash Takshi <> University of South Florida
    From: Srinivas Katkoori <>

3. Paper Submission Deadlines
    From: Debjit Sinha <>

4. Upcoming Conferences and Symposia
    From: Debjit Sinha <>

5. Upcoming Funding Opportunities
    From: Prabhat Mishra <>

6. Call for Papers: International Conference on VLSI Design and International Conference on Embedded Systems
    From: Sachin S. Sapatnekar <>

7. Call for participation: ACM SIGDA CADathlon 2012
    From: Sudeep Pasricha <>

8. Call for participation: 2012 CAD Contest
    From: Zhuo Li <>

9. Call for Abstracts: VLSI-SoC 2012 PhD Forum
    From: Matthew Guthaus <>
Comments from the Editors

Dear ACM/SIGDA members,

In this issue, we have a very interesting article on Organic FETs.
If you are interested in contributing to this column in
the future, please contact Srinivas Katkoori <>.
An article only needs to be about 1 page long with several references.
All articles are included in the ACM digital library and there is no
restriction for the reproduction of the article for printed
publication later.

Sudeep Pasricha, E-Newsletter Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Srinivas Katkoori, E-Newsletter Associate Editor
Prabhat Mishra, E-Newsletter Associate Editor

Back to Contents


"China, U.S. lead innovation, Europe nowhere, says survey"
China and the United States are the two countries most likely to come up with
"disruptive technology breakthroughs" with a global impact in the next two to
four years, according to a survey conducted by auditor and consultancy KPMG.

"Intel announces another university research center"
Intel Corp. Tuesday (June 26) announced its seventh Intel Science and Technology
Center (ISTC) will focus on social computing and be based at the University of
California, Irvine. As with other ISTCs, Intel plans to sink $15 million in the
UC Irvine ISTC over a five-year period, Rattner said. The announcement of the
seventh ISTC completes the company's commitment, announced last year, to invest
$100 million in the ISTC program over five years.

"Patent snafus could delay new video codec"
The H.265 High Efficiency Video Coding (HEVC) standard is about to be ratified,
promising a new generation of higher resolution and more compact digital video
products. The bad news is chip makers are afraid to design products using it.
Vendors may have filed as many as 500 patents relating to the H.265 HEVC technology.
But so far just who owns what and how much they expect in royalties is unclear. The
current video codec, H.264, has been the basis of digital video products such as
camera phones and digital video recorders for eight years. Thanks to a patent
pool created by the MPEG Licensing Authority, the licensing rate is said to be a
flat 25 cents per chip maximum, capped at about $12 million per vendor.

"Facebook likes wimpy cores, CPU subscriptions"
Facebook could start running--at least in part--on so-called wimpy server CPU
cores by the second half of 2013. Long term, the company wants to move to a
systems architecture that lets it upgrade CPUs independent of memory and networking
components, buying processors on a subscription model. The social networking giant will
not reveal whether it will use ARM, MIPS-like or Atom-based CPUs first. But it does plan
to adopt so-called wimpy cores over time to replace some of the workloads currently run
on more traditional brawny cores such as Intel Xeon server processors.

"IBM re-takes lead in Top 500 computers"
IBM re-took the lead on the latest edition of the list of the world’s
Top 500 supercomputers with Sequoia, a 16.32 petaflops system packing more
than 1.5 million custom Power cores. It is based on the same IBM BlueGene/Q
architecture used in three other top ten systems which also were the most
power efficient on the list. Installed at the U.S. Department of Energy’s
Lawrence Livermore National Laboratory, Sequoia consumes a whopping 7.89
MW of power, second only to the previous top system, Japan’s K Computer
which gulps 12.65 MW. Nevertheless the BlueGene/Q architecture is the most
power efficient on the list delivering 2,099 Mflops/Watt.

"TI details TSV integration in 28-nm CMOS"
Texas Instruments Inc. Wednesday (June 13) detailed progress in integrating
through-silicon-vias (TSVs) into the company's advanced 28-nm CMOS process
with little or no impact on nearby transistors. In a paper due to be presented
at the 2012 Symposia on VLSI Technology and Circuits in Honolulu, Hawaii, TI
researchers were set to show results indicating minimal effect on transistors
within 4 microns of TSV placement. The paper that researchers were to present
also describes the use of nanobeam diffraction to measure near-TSV silicon
strain on fully processed wafers to study the net effect of stressors.

"OLEDs are hitting their stride this year in all segments"
OLEDs are finally living up to their long-promised potential and the next few
years will present plenty of opportunities for organic light emitting diode
materials suppliers to break out of their niche, specialty status. That's
according to a new report by market research firm NanoMarkets. The growth
of Samsung's Galaxy smartphone products have exceeded iPhones in the first
quarter of 2012. What's more OLED TVs from both LG and Samsung are entering
the market this summer and fall, and other manufacturers are likely to follow
in the near term.

"Legislation seeks to relax restrictions on tracking fake chips"
Three lawmakers have proposed legislation aimed at stemming the flow of
counterfeit semiconductors into the U.S., a growing threat to the nation’s
national security and critical infrastructure. The legislation introduced by
Reps. Michael McCaul (R-Texas), Howard McKeon (R-Texas) and William Keating
(D-Mass.) seeks to reverse the U.S. Customs and Border Protection’s
policy that limits chip makers’ access to photographs of trademarks on
suspected fake chips. H.R. 6012 would again allow chip makers to examine
photographs showing identifying information on suspect chips to determine
their authenticity.

"Research shows more strain can improve transistors"
Researchers from France and Switzerland have shown that much higher stresses
than previously applied can improve the hole mobility in p-type silicon
beyond what had previously been thought possible. The results could change
the way chip companies seek to engineer transistors at the leading edge,
one of the researchers claimed. Chip manufacturers already use strain to
improve the electron and hole mobility in n- and p-type transistors. The
use of stress to produce higher performing devices had previously thought to
have reached a limit and that the use of exotic materials such as compound
semiconductor layers or carbon sheets would be the next step in improving
transistor and IC performance.

"Fab tool spending to fall 9% in 2012, says Gartner"
Worldwide wafer fab equipment spending is on pace to total $33 billion in 2012,
a decline of 9 percent from $36.2 billion in 2011, according to market research
firm Gartner Inc. Gartner (Stamford, Conn.) forecasts that fab tool spending
will grow 7 percent in 2013 to reach $35.4 billion, still below the 2011 level.

"Researchers try vacuum transistors at low voltage"
Researchers at the University of Pittsburgh have come up with a device
structure that allows a switch back to vacuum, in contrast to the solid-state,
as the medium for electron transport in transistors. The team is proposing a
MOS vertical structure with a triple layer of metal/silicon dioxide/silicon
exposed on the side by a deep trench. The metal and silicon layers form the
anode and cathode of the device, separated by the insulating silicon dioxide,
and the electron transport occurs in the vertical direction through the vacuum.

"Infineon leads power chip market ranking, says IMS"
The power semiconductor market grew by 9 percent to just under $18 billion
in 2011, with Infineon Technologies AG at the top of the ranking, according
to market analyst IMS Research Ltd.

Back to Contents

What is an Organic FET?

Arash Takshi, University of South Florida

An organic FET or OFET is a field-effect transistor which is made of
an organic semiconductor instead of regular semiconductors such as
silicon or GaAs. Because of the mechanical properties of the organic
materials, OFETs are suitable for making flexible electronics such as
rollable displays and wearable electronics [Bonfiglio 05]. Also,
simple methods of fabrication of organic transistors have made them
suitable for low cost electronics such as radio frequency
identification (RFID) tags. In principle, OFETs can be fabricated by
printing layers of an organic semiconductor, an insulator, and a
conductive material on a substrate. This method of fabrication does
not need the expensive cleanroom facilities and can print devices and
circuits in a roll-to-roll process like printing newspapers
[Zipperer10]. In addition, printing is an efficient method for
fabricating large-area devices like TV screens. Printing electronic
devices and circuits as easy as we use an office printer will
revolutionize the electronic industry and open new markets. For
example, the printed barcodes on the products would be replaced with
printed RFID tags, which can respond to a scanner instantly. Using
this technology, shopping in a supermarket would be as easy as filling
up your shopping cart and walking through the scanner gate and picking
your credit card receipt before leaving the store. Since transistors
are the building blocks of almost all electronic circuits, development
of printable organic transistors with reasonable characteristics is

Like all FET devices, an OFET has a gate terminal through which the
current in the channel (between drain and source terminals) can be
controlled. The gate is isolated from the organic semiconductor by a
layer of an insulating material. A thin film of an organic
semiconductor can be deposited with various methods such as vacuum
evaporation, solution casting, printing, and spin coating
[Reese04]. The characteristic of an OFET depends on the applied
materials, fabrication method, and the device geometry.

Organic chemicals such as polymers and plastics are often insulating
materials. However, an organic compound with a conjugated structure
(alternative single and double bonds between the carbon atoms) behaves
like a semiconductor. There are two main categories of organic
semiconductors: conducting polymers and small organic molecules. The
bulk properties of these two types of semiconductors are somehow
similar, but the deposition methods for them are different. The
amorphous structure of a thin film organic semiconductor results in
narrow energy bands (conduction and valance bands) with high density
of localized energy states in the band gap of the semiconductor.
Therefore, the mobility of carriers in the organic materials is
significantly lower than that in crystalline semiconductors
(e.g. silicon). The low mobility affects the speed of the
transistor. Generally, OFETs are too slow for building a
microprocessor, but they are fast enough for simple logic
circuits. The best method for making a film from small organic
molecules is the vacuum evaporation. Controlling the deposition rate,
a well-ordered molecular film can be produced with carrier mobility
only one order of magnitude less than silicon [Smith09]. However,
this method of deposition is expensive. Functionalized small molecules
or conducting polymers can be dissolved in a solvent to make an ink of
the semiconductor. Various methods of printing, including inkjet and
silk screen printings, can be used to make a film of the
semiconductor. These methods are much easier than the conventional
semiconductor fabrication methods, and it is suitable for large-area
electronic circuits/devices. The problem is in the quality of the
printed film which affects the mobility of carriers in the
semiconductor. A few simple techniques such as surface treatment prior
to the printing and post deposition alignment can largely improve the
quality of the film [Sirringhaus03]. Nevertheless, the quality never
reaches to the vacuum evaporation for small molecules.

In an OFET, the drain and source are in direct contact with the
semiconductor film, and the gate is on an insulating layer on top of
the semiconductor. Electrode contacts are usually made of metals,
which are patterned by photolithography method either before or after
semiconductor deposition. The recent developments in printing metal
nanoparticles have opened opportunities to make fully printed
transistors using metal, insulator, and semiconductor inks
[Ko07]. Putting the drain and source contacts on top or bottom of the
semiconductor affects the transconductance (gain) of the device. Also,
the thicknesses of the semiconductor and insulating layers change the
transistor characteristics, particularly the threshold voltage. A very
thin film of an insulator with high dielectric constant is required to
achieve a low-threshold voltage. A low-threshold voltage is required
to make a circuit with low voltage power supply. The early devices
made with thick insulator used to run with voltages larger than 40
V. Developing the printing techniques for depositing thin films of
insulators, the voltage has dropped to about 5 V in new OFETs

In conclusion, printable organic transistors are suitable for flexible
and low cost electronic circuits. Overcoming technical issues such as
voltage operation and encapsulation of the devices, various organic
electronic products will be available soon.


[Bonfiglio 05] A. Bonfiglio, D. De Rossi, T. Kirstein, I. R. Locher,
F. Mameli, R. Paradiso, and G. Vozzi, "Organic field effect
transistors for textile applications," IEEE Transactions on
Information Technology in Biomedicine, 2005.

[Zipperer10] D. Zipperer, "Roll-To-Roll Printed Electronics", Digital
Fabrication 2010, Austin, Texas, USA.

[Reese04] C. Reese, M. Roberts, M.-m. Ling, and Z. Bao, "Organic thin
film transistors," Materials Today, vol. 7, pp. 20-27, 2004.

[Shaw01] J. M. S. Shaw, P. F., "Organic electronics: Introduction,"
IBM Journal of Research & Development, 2001.

[Smith09] J. Smith, R. Hamilton, I. McCulloch, M. Heeney,
J. E. Anthony, D. D. C. Bradley, and T. D. Anthopoulos, "High mobility
p-channel organic field effect transistors on flexible substrates
using a polymer-small molecule blend," Synthetic Metals, 2009.

[Sirringhaus03] H. Sirringhaus, "Organic semiconductors: An
equal-opportunity conductor," Nat Mater, 2003.

[Ko07] S. H. Ko and et al., "All-inkjet-printed flexible electronics
fabrication on a polymer substrate by low-temperature high-resolution
selective laser sintering of metal nanoparticles," Nanotechnology,

[Ortiz09] R. o. P. Ortiz, A. Facchetti, and T. J. Marks, "High-k
Organic, Inorganic, and Hybrid Dielectrics for Low-Voltage Organic
Field-Effect Transistors," Chemical Reviews, 2009.

Back to Contents

Paper Submission Deadlines

VLSI'13 - Int'l Conference on VLSI Design
Pune, India
Deadline: Jul 2, 2012
Jan 5-10, 2013

ASP-DAC'13 - Asia and South Pacific Design Automation Conference
Yokohama, Japan
Deadline: Jul 13, 2012
Jan 22-25, 2013

DATE'13 - Design Automation and Test in Europe
Grenoble, France
Deadline: Sep 9, 2012
Mar 18-22, 2013

ISSCC'13 - Int'l Solid-State Circuits Conference
San Francisco, CA
Deadline: Sep 10, 2012
Feb 17-21, 2012

ISQED'13 - Int'l Symposium on Quality Electronic Design
Santa Clara, CA
Deadline: Sep 12, 2012
Mar 11-13, 2013

Back to Contents

Upcoming Conferences and Symposia

ASQED'12 - Asia Symposium on Quality Electronic Design
Kuala Lumpur, Malaysia
Jul 10-12, 2012

MEMOCODE'12 – Int’l Conference on Formal Methods and Models for Codesign
Arlington, VA
Jul 16-18, 2012

PACT'12 - Int'l Conference on Parallel Architectures and Compilation
Minneapolis, MN
Sep 21-25, 2012

BodyNets'12 – Int’l Conference on Body Area Networks
Oslo, Norway
Sep 24-26, 2012

VLSI-SoC’12 – Int’l Conference on Very Large Scale Integration and System on Chip
Santa Cruz, CA
Oct 7-12, 2012

ESWEEK'12 - Embedded Systems Week (CASES, CODES+ISSS, and EMSOFT)
Tampere, Finland
Oct 7-12, 2012

Wireless Health’12
San Diego, CA
Oct 22-25, 2012

ICCAD’12 – Int’l Conference on Computer-Aided Design
San Jose, CA
Nov 5-8 2012

HLDVT’12 – Int’l High-Level Design, Validation and Test Workshop
Huntington Beach, CA
Nov 9-10, 2012

BIOCAS'12 - Biomedical Circuits and Systems Conference
Hsinchu, Taiwan
Nov 28-30, 2012

MICRO'12 - Int'l Symposium on Microarchitecture
Vancouver, Canada
Dec 1-5, 2012

ICFPT'12 - Int'l Conference on Field-Programmable Technology
Seoul, Korea
Dec 10-12, 2012

ICPADS'12 - Int'l Conference on Parallel and Distributed Systems
Singapore, Singapore
Dec 17-19, 2012

HiPC'12 - Int'l Conference on High Performance Computing
Pune, India
Dec 18-21, 2012

ISED’12 – Int’l Symposium on Electronic System Design
Kolkata, India
Dec 19-22, 2012

HiPEAC'13: Int'l Conference on High Performance Embedded Architectures & Compilers
Berlin, Germany
Jan 21-23, 2013 hipeac2013

Back to Contents

Upcoming Funding Opportunities


Office of Naval Research (ONR) Summer Faculty Research Program
Deadline: December 05, 2012

National Defense Science and Engineering Graduate (NDSEG) Fellowship Program
Deadline: December 16, 2012

Office of Naval Research (ONR) Sabbatical Leave Program
Deadline: Continuous

Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Deadline: Continuous


High-Assurance Cyber Military Systems (HACMS)
Deadline: July 10, 2012

Microsystems Technology Office-Wide Broad Agency - DARPA-BAA-10-35
Deadline: September 1, 2012


Robust Computational Intelligence - AFOSR-BAA-2012-01
Deadline: Continuous

Systems and Software - AFOSR-BAA-2012-01
Deadline: Continuous

ERDC BAA - Computational Science and Engineering (ITL-1)
Deadline: Continuous

Advanced Distributed Sensor Technologies - BAA 57-09-06
Deadline: Continuous

Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
Deadline: Continuous

High Performance Computing on Massively Parallel Architectures (BAA 64-09-01)
Deadline: Continuous

ASEE-NRL Postdoctoral Fellowship Program
Deadline: N/A

Multidisciplinary University Research Initiative (MURI)
Deadline: September 15, 2012


Resilient Extreme-Scale Solvers ("RX-Solvers")
Deadline: August 13, 2012

Early Career Research Program
Deadline: September 01, 2012

Director's Postdoctoral Fellows
Deadline: Continuous

Postdoctoral Appointments
Deadline: N/A

Sabbaticals and Faculty Appointments
Deadline: continuous

McDonnell Foundation

Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Deadline: continuous

Alfred P. Sloan Foundation

Sloan Research Fellowships
Deadline: September 15, 2012


Computational and Data-Enabled Science and Engineering (CDS&E) in Engineering (CDS&E-ENG)
Deadline: July 03, 2012

Core Techniques and Technologies for Advancing Big Data Science & Engineering (BIGDATA)
Deadline: July 11, 2012

Cyberlearning: Transforming Education (Cyberlearning)
Deadline: July 16, 2012

Faculty Early Career Development (CAREER) Program
Deadline: July 23-25, 2012

Failure-resistant systems (FRS)
Deadline: July 26, 2012

Research Experiences for Undergraduates (REU)
Deadline: September 15, 2012

Research and Evaluation on Education in Science and Engineering (REESE)
Deadline: Continuous

Back to Contents

Call for Papers: International Conference on VLSI Design and International Conference on Embedded Systems


January 5-9, 2013
Pune, India

THEME: Green Technologies - A New Era for Electronics

Submissions (Paper/Tutorial/Special Sessions): July 2, 2012
Acceptance of notification: September 7, 2012
Camera ready paper due: October 1, 2012

This joint conference is a forum for researchers and designers to
present and discuss current topics in VLSI design, electronic design
automation, embedded systems, and enabling technologies. Two days of
tutorials will be followed by three days of regular paper sessions,
special sessions, and embedded tutorials. Industry presentation
sessions along with exhibits, panel discussions, Design Contest, and
Education Forum round off the program. The theme for the conference is
"Green Technologies - A New Era for Electronics," which explores the
ability of VLSI and embedded circuits and systems to positively impact
the environment. Example areas under the theme include (but are not
restricted to) designing energy-efficient VLSI circuits, improving the
efficiency of energy-hungry applications such as data centers,
developing intelligent monitoring and control systems such as smart
grids, and using integrated circuits or embedded systems to leverage
novel green technologies.

TOPICS OF INTEREST: Papers are invited on previously unpublished results
in various categories related to VLSI design, electronic design,
embedded systems, and enabling technologies. For details, please refer
to the conference website.

relevance to this conference should be submitted as two-page abstracts.
On acceptance, authors are required to submit full regular papers.

HALF-DAY AND FULL-DAY TUTORIALS: Continuing a tradition of running a
highly successful series of tutorials, the first two days of the
conference will be dedicated to tutorials on recent topics in VLSI
design, EDA, VLSI technology, and embedded systems. Tutorial proposals
should be submitted through the conference website by July 2, 2012.

PANELS: Proposals must be submitted with an abstract, and a list of

SUBMISSIONS: All submissions should be made electronically via the
conference website by July 2, 2012. Your manuscript should clearly state
the novel ideas, results and applications of the contribution. Paper
submissions will undergo a double-blind review. Papers must be in PDF
format and not exceed 6 single-spaced pages including figures and
references in two-column IEEE conference paper format. Papers exceeding
the 6 page limit or identifying the authors will be rejected without
review. All submissions of papers and proposals will imply that, if
selected, they will be presented at the conference in person. Hence,
approvals from parent organizations must be obtained before the
submissions are made.


Technical Program Co-chairs:
Alok Jain ( and Sachin Sapatnekar (

Nagi Naganathan (

Back to Contents

Call for participation: ACM SIGDA CADathlon 2012

ACM SIGDA CADathlon 2012
Sunday, November 4

The CADathlon is a challenging, all-day, programming competition
focusing on practical problems at the forefront of Computer-Aided
Design, and Electronic Design Automation in particular. The contest
emphasizes the knowledge of algorithmic techniques for CAD
applications, problem-solving and programming skills, as well as

In its eleventh year as the "Olympic games of EDA," the contest brings
together the best and the brightest of the next generation of CAD
professionals. It gives academia and the industry a unique perspective
on challenging problems and rising stars, and it also helps attract
top graduate students to the EDA field.

The contest is open to two-person teams of graduate students
specializing in CAD and currently full-time enrolled in a
Ph.D. granting instit ution in any country. Students are selected
based on their academic backgrounds and their relevant EDA programming
experiences. Travel grant s are provided to qualifying students.The
CADathlon competition consists of six problems in the following areas:

(1) Circuit analysis
(2) Physical design
(3) Logic and behavioral synthesis
(4) System design and analysis
(5) Functional verification
(6) Bio-EDA

More specific information about the problems and relevant research
papers will be released on the Internet one week prior to the
competition. The writers and judges that construct and review the
problems are experts in EDA from both academia and industry. At the
contest, students will be given the problem statements and example
test data, but they will not have the judges' test data. Solutions
will be judged on correctness and efficiency. Where appropriate,
partial credit might be given. The team that earns the highest score
is declared the winner. In addition to handsome trophies, the first
place team's prize is a $2,000 cash award. The second place team's
prize is a $1,000 cash award.

Contest winners will be announced at the ICCAD Opening Session on
Monday morning and celebrated at the ACM/SIGDA Dinner and Member
Meeting on Monday evening.

The CADathlon competition is sponsored by ACM/SIGDA and several
Computer and EDA companies. For detailed contest information and
sample prob lems from last year's competition, please visit the ACM/
SIGDA website at


October 3 Participation request for submission due
October 8 Notification of acceptance


Chair, Jarrod Roy,
Vice Chair, Asst. Prof. Sudeep Pasricha,
Vice Chair, Assoc. Prof. Srinivas Katkoori,
Vice Chair, Sudarshan Banerjee,

Back to Contents

Call for participation: 2012 CAD Contest

Call for participation

The annual CAD Contest in Taiwan, sponsored by the Ministry of Education
(MOE), has been held for 12 consecutive years and has successfully boosted
the EDA research momentum in Taiwan. In 2012, we continue this great
tradition and internationalize it under the joint sponsorship of IEEE CEDA
and Taiwan MOE. The new contest, 2012 CAD Contest at ICCAD, is open
worldwide to have more significant contributions to our global EDA
community. You are invited to participate!


In the first year (2012), we design three contest problems covering three
distinct areas:

1. Finding the minimal logic difference for functional ECO contributed by
Taiwan Cadence Design Systems, Inc.
2. Design hierarchy aware routability-driven placement contributed by IBM
3. Fuzzy pattern matching for physical verification contributed by Mentor
Graphics Corp.


1. The contestants should be university students.
2. Contestants must register by August 1, 2012.
3. Changes of team members, advisors or topics should be made by the
deadline of registration.

Evaluation and ranking

1. Each topic is ranked separately.
2. The quality metrics are determined by the problem specifications,
including correctness, runtime and memory usage.
3. Each submitted program will be evaluated by the announced benchmarks and
hidden benchmarks.
4. The officially supported programming language will be C/C++. For other
languages, please check with the contest organizers first. MATLAB is
prohibited for use in the contest.
5. The library that can be used in the contest is the standard C/C++

6. System specification:

Linux version: TBD
Gcc version: TBD
GNU libc version: TBD

Tentative Contest Schedule

1. Call for participation April 25, 2012.
2. Official website open April 25, 2012
3. Problem description announcement April 25, 2012
4. Registration deadline August 1, 2012
5. Alpha submission August 8, 2012
6. Submission deadline September 24, 2012
7. Final announcements November 2012 (at ICCAD)

Other Information

1. For any other inquiries, please send emails
2. Please add "ICCAD2012_Contest" to the subject line for any emails
regarding the contest.
3. Any update will be announced on contest website:
4. There may be a special session organized for the contest at ICCAD 2012
(we will be notified by the end of May). This session includes three
presentations from the contest organizers for the three contest problems and
the award ceremony.


1. Contest chair:
Yih-Lang Li (National Chiao Tung University, Taiwan)
2. Co-chairs:
Iris Hui-Ru Jiang (National Chiao Tung University, Taiwan)
Zhuo Li (IBM, Corp.)
3. Topic chairs:
Jane Wang (Taiwan Cadence Design Systems, Inc.)
Natarajan Viswanathan (IBM Corp.)
Andres Torres (Mentor Graphics Corp.)


1. IEEE CEDA (Technical sponsorship)
2. Taiwan Ministry of Education (Financial sponsorship)

Back to Contents

Call for Abstracts: VLSI-SoC 2012 PhD Forum

Call for Abstracts

at the

20th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
October 7-10, 2012
Santa Cruz, CA, USA
Dream Inn Hotel

VLSI-SoC 2012 is the 20th in a series of international conferences
sponsored by IFIP TC 10 Working Group 10.5, IEEE CEDA and IEEE CASS
that explores the state-of-the-art and the new developments in the
field of Very Large Scale Integration (VLSI) and System-on-Chip
(SoC). VLSI-SoC 2012's Ph.D. Forum is a poster session dedicated to
the exchange of ideas and experiences of Ph.D. students from different
parts of the world. Elected Ph.D. students have an opportunity to
discuss their thesis and research work with specialists with the
community. This exchange offers a good opportunity for students to
receive valuable feedback and gain exposure in the job
market. Furthermore, this forum also provides a great chance for
industry officials to meet junior researchers, giving an avenue for
incorporating the latest research developments into their companies.

Topics of interest include but are not limited to:
* Analog and Mixed-Signal IC Design
* Circuits and Systems for Micro-sensing Applications
* 3-D Integration, Physical Design, Compact Modeling, and
Electromagnetic Analysis
* Design for Variability, Reliability, Fault Tolerance, Test
* Digital Signal Processing and Image Processing IC Design
* New Devices, MEMS and Microsystems
* Prototyping, Validation, Verification, Modeling and Simulation
* System-On-Chip Design, Digital Architectures
* Embedded Systems Design and Real-Time Systems
* Reconfigurable Systems, Compiler
* Logic and High-Level Synthesis
* Low-Power and Thermal-aware Design


PhD Forum Submission: July 1, 2012
Notification of Acceptance: July 15, 2012


A 1 page abstract of the complete dissertation should be submitted via
the EasyChair conference submission system:

Eligibility: The author must have completed at least one year of a
Ph.D. program. Abstract format:

Presentation: Posters will be presented during a full one-hour Poster
Session. Accepted abstracts will NOT be published by IEEE or ACM.


IFIP WG 10.5
IEEE Circuits and Systems Society
UC Santa Cruz

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