ACM SIGDA/IEEE CEDA University Demonstration (UD, previously University Booth) is an excellent opportunity for university researchers to showcase their results and to interact with participants at the Design Automation Conference (DAC). Presenters and attendees at DAC are especially encouraged to participate, but participation is open to all members of the university community. The demonstrations include new EDA tools, EDA tool applications, design projects, and instructional materials.
The University Demonstration will be held together with the Ph.D. Forum at DAC.
Date: June 22-25, 2025
Location: Moscone Center West, San Francisco
SUBMISSION GUIDELINES
Submission should be made online at the Submission Site. Please upload a single PDF file that has the following:
Title of your demonstration
List of authors with their affiliations
An extended abstract of up to 2 pages, excluding figures and references
A YouTube link to a 5-minute online video teaser. If you are not able to upload it to YouTube, please include another link to your video teaser.
Notification of Acceptance will be on Jun 5, 2025.
AWARD AND STUDENT SUPPORT INFORMATION
There will be three “University Demo Best Demonstration” awards and travel support for presenters up to $700 for each team to attend the University Demonstration event in person for the accepted submissions.
The presenter will be provided full registration to this year’s DAC.
The winners will be announced at the conference after the demonstration. The presenter will only be eligible for travel support if he/she does not receive any travel support from other events at DAC such as Ph.D. Forum or Young Fellowship.
First Place
$1000
Second Place
$750
Third Place
$500
The teams whose submissions got accepted should do the following for UDDAC 2024.
1. The presenter’s name and title
2. In-person video demonstrations are mandatory and should include a brief title sequence identifying the name of the research group and university, the team members, and stating “University Demonstration at DAC 2024.” Otherwise, there is complete freedom in how a group wishes to present its work.
Organizing Committee
Chair
Sumitha George, North Dakota State University. e-mail
HACK@DAC 2023 consists of 2 phases, a Qualifying Round and a Live Round. The Qualifying Round was open to all participants and ended in mid-May. Top teams from the Qualifying Round were invited to participate in the Live Competition on July 9-10 at the Design Automation Conference (#DAC60) in San Francisco, CA. Teams had 48 hours to find and exploit as many security vulnerabilities in the “buggy SoC” provided by the competition organizers. Points were awarded to teams that correctly identified security vulnerabilities in the design. Bonus points were earned when teams demonstrated clever use of automation in vulnerability detection and/or exploitation. Teams with the highest scores win.
DAC Award Ceremony on July 13, 2023.
Not Your Typical Capture-the-Flag (CTF)
To deliver an immersive, hands-on pre-silicon hacking experience, we prepared a sophisticated “buggy SoC” that incorporated industry-scale security features along with common security vulnerabilities that were inspired by real-world product issues. In addition, we enabled each team with a set of powerful commercial-grade EDA tools in the cloud, while providing options for teams to deploy their own custom tools. Participants in all SoC hacking experience levels were covered.
Behind the Scenes
The HACK@DAC organizing team is made up of industry and academia experts. A big shout-out goes to the team for their flawless execution and outstanding collaboration, working tirelessly since the beginning of the year.
CADathlon 2023 will be held as an in-person event.
Sunday, Oct. 29, 2023 08:00 AM – 05:00 PM, In-Person
Gallery Ballroom, The Hyatt Regency San Francisco Downtown SoMa, San Francisco, CA, USA
The contest is open to two-person teams of undergraduate/graduate students specializing in CAD and currently full-time enrolled in a Ph.D. granting institution in any country. Students are selected based on their academic backgrounds and their relevant EDA programming experiences. Partial or full travel grants are provided to qualifying students. CADathlon competition may consist of six problems in the following areas:
Circuit Design & Analysis
Physical Design & Design for Manufacturability
Logic & High-Level Synthesis
System Design & Analysis
Functional Verification & Testing
Future technologies (Bio-EDA, Security, AI, etc.)
More specific information about the problems and relevant research papers will be released on the Internet one week prior to the competition. The writers and judges that construct and review the problems are experts in EDA from both academia and industry. At the contest, students will be given the problem statements and example test data, but they will not have the judges’ test data. Solutions will be judged on correctness and efficiency. Where appropriate, partial credit might be given.
The team that earns the highest score is declared the winner. In addition to handsome trophies, the first place and the second place teams receive cash award, and the contest winners will be announced at the ICCAD conference.
Cash Prize
First place award: 1500 per person
Second place award: 750 per person
Participation Request (please submit via Google Form)
Important dates
October 10th, 2023: Participation request form due
October 14th, 2023: Participation acceptance announcement
October 22th, 2023: Release of topic/hardware details
SIGDA Live is a series of webinars, launched monthly or bi-monthly, on topics (either technical or non-technical) of general interest to the SIGDA community. The talks in general fall on the last Wednesday of a month, and last about 45 minutes plus 15 minutes Q&A. Speaker and topic nominations are welcome and should be sent to sigdalive@gmail.com. All past talks are archived through our Youtube channel at: https://www.youtube.com/channel. Each year we recognize one speaker with the “Most Influential Speaker of the Year” award.
Organizers: Yiyu Shi (University of Notre Dame), Qinru Qiu (Syracuse University)
Technical support: Bei Yu (Chinese University of Hong Kong)
The DAC System Design Contest focuses on object detection and classification on an embedded GPU or FPGA system. Contestants will receive a training dataset provided by Baidu, and a hidden dataset will be used to evaluate the performance of the designs in terms of accuracy and speed. Contestants will compete to create the best performing design on a Nvidia Jetson Nano GPU or Xilinx Kria KV260 FPGA board. Grand cash awards will be given to the top three teams. The award ceremony will be held at the 2023 IEEE/ACM Design Automation Conference.
The Student Research Forum at the ASP-DAC is renovated from a traditional poster session hosted by ACM SIGDA for PhD students to present and discuss their dissertations with experts in the design automation community. Starting from 2015, the forum includes both PhD and MS students, offering great opportunity for the students to establish contacts for their future career. In addition, the forum helps the companies and academic institutes to get an overview of the latest research and discover the extraordinary candidates for their employment.
This Year’s Awards (2022)
Best Poster – Research Intelligent Circuit Design and Implementation with Machine Learning in EDA Zhiyao Xie, Duke University
Best Poster – Presentation Algorithm-Hardware Co-design of Transformer on FPGA Devices Xinyi Zhang, University of Pittsburgh
Most Popular Poster ASBP: Automatic Structured Bit-Pruning for RRAM-based NN Accelerator Songyun Qu, Chinese Academy of Sciences
Call for Submission: SIGDA Student Research Forum at ASP-DAC 2021 (SRF@ASP-DAC 2021)
Considering ASP-DAC 2021 is going virtual due to COVID-19, SRF@ASP-DAC 2021 will be held as a virtual forum. The forum welcomes all students, professors and industrial professionals from the relevant research community. The student author of each accepted submission by the forum is required to have a registration to ASP-DAC 2021 at least at the full student rate. The forum will provide financial support equivalent to the full student rate for each accepted submission.
ELIGIBILITY
Students must be within 1 year (M.S.) or 2 years (Ph.D.) of dissertation completion or have completed their dissertation during the last 12 months.
Dissertation topic must be relevant to the ASP-DAC community.
Previous ASP-DAC forum presenters are not eligible.
Students who have presented previously at DAC/DATE PhD forums are eligible.
Only students with at least one published or accepted conference, symposium or journal “full” paper are eligible for awards.
Students must attend the forum virtually to present the poster in person without substitute presentations, or else please contact the SRF Chair in advance.
SUBMISSION REQUIREMENTS A two-page PDF abstract of the dissertation (in two-column format, using 10pt. fonts and single-spaced lines), including name, institution, adviser, contact information, estimated (or actual) graduation date, whether the work has been presented at DAC PhD Forum or DATE PhD Forum, as well as figures and bibliography (if applicable). The two-page limit on the abstract will be strictly enforced: any material beyond the second page will be ignored by the reviewers. Each accepted abstract has to prepare a poster and a short video presentation, and the student has to attend the forum virtually for real-time interactions.
To be considered for awards, a student must explicitly indicate, in the title of the two-page abstract, the venues for which the work was published or accepted, and a list of all papers authored or co-authored by the student should be included in the bibliography of the two-page abstract. The papers must be related to the dissertation topic. Those on topics unrelated to the dissertation abstract will not be considered.
IMPORTANT DATES Submission Deadline: November 30, 2020 (firm) Date of Acceptance Notification: December 14, 2020 Poster and Short Video Submission Deadline: January 5, 2021 Forum Date: January 19, 2021
CONTACT INFORMATION For queries, please send an e-mail to Prof. Weichen Liu (liu [at] ntu.edu.sg). Please include “SRF@ASP-DAC 2021” in the subject of your email.
Organizers
Chair: Weichen Liu, Nanyang Technological University, Singapore Co-Chairs: Lei Jiang, Indiana University Bloomington, US Yaoyao Ye, Shanghai Jiao Tong University, China Secretariat: Jun Zhou, Nanyang Technological University, Singapore Technical Committee: Hiromitsu Awano, Kyoto University, Japan Donkyu Baek, Chungbuk National University, Korea Ateet Bhalla, Independent Technology Consultant, India Yuan-Hao Chang, Academia Sinica, Taiwan Wanli Chang, University of York, UK Xianzhang Chen, Chongqing University, China Yi-Jung Chen, National Chi Nan University, Taiwan Xiang Chen, George Mason University, US Haibao Chen, Shanghai Jiao Tong University, China Sudipta Chattopadhyay, Singapore Univ. of Technology and Design, Singapore Hsiang-Yun Cheng, Academia Sinica, Taiwan Luan Huu Kinh Duong, Nanyang Technological University, Singapore Shao-Yun Fang, National Taiwan University of Science and Technology, Taiwan Ann Gordon-Ross, University of Florida, US Chien-Chung Ho, National Chung Cheng University, Taiwan Weiwen Jiang, University of Notre Dame, US Yukihide Kohira, The University of Aizu, Japan Hyung-Gyu Lee, Daegu University, Korea Sicheng Li, Hewlett Packard Labs, US Yongfu Li, Shanghai Jiao Tong University, China Qingan Li, Wuhan University, China Chun-Han Lin, National Taiwan Normal University, Taiwan Ren-Shuo Liu, National Tsing Hua University, Taiwan Jaehyun Park, University of Ulsan, Korea Muhammad Shafique, New York University Abu Dhabi, UAE Liang Shi, East China Normal University, China Donghwa Shin, Soongsil University, Korea Masashi Tawada, Waseda University, Japan Hoeseok Yang, Ajou University, Korea Ming-Chang Yang, The Chinese University of Hong Kong, China Lei Yang, University of New Mexico, US Bei Yu, The Chinese University of Hong Kong, China Qian Zhang, University of California, Los Angeles, US ASP-DAC liaison: Masashi Tawada, Waseda University, Japan Yukio Mitsuyama, Kochi University of Technology, Japan
The Ph.D. Forum at the Design Automation Conference is a poster session hosted by ACM SIGDA and IEEE CEDA for Ph.D. students to present and discuss their dissertation research with people in the EDA community. It has become one of the premier forums for Ph.D. students in design automation to get feedback on their research and to connect with other members of the community. It also enables both, academicians and industry, to see the best graduating students in one place. Presentations are selected through a scientific evaluation by an expert committee consisting of academia and industry. The forum is open to all members of the design automation community and is free-of-charge. It is co-located with DAC, but a DAC registration is not required in order to attend this event.
Submission Process
In order to select the presentations to be featured at the DAC Ph.D. Forum, we are seeking contributions from students who are currently working on their Ph.D. or have recently completed their Ph.D. Corresponding applications have to be submitted through EasyChair and need to include the following two documents:
A two-page PDF abstract of the dissertation (in two-column format, using 10-11 pt. fonts and single-spaced lines), including name, institution, advisor, contact information, estimated (or actual) graduation date, whether the work has been presented at the ASP-DAC Ph.D. Forum or the DATE Ph.D. Forum, as well as figures, and bibliography (if applicable). The two-page limit on the abstract will be strictly enforced: any material beyond the second page will be truncated before sending to the reviewers. Please include a description of the supporting paper, including the publication forum. A list of all papers authored or co-authored by the student, related to the dissertation topic and included in the two-page abstract, will strengthen the submission.
A published (or accepted) paper, in support of the submitted dissertation abstract. The paper must be related to the dissertation topic and the publication forum must have a valid ISBN number. It will be helpful, but is not required, to include your name and the publication forum on the first page of the paper. Papers on topics unrelated to the dissertation abstract or not yet accepted will not be considered during the review process.
Please include the supporting paper with the abstract in one PDF file and submit the single file (there are many free utilities available online which can merge multiple PDF files into a single file if necessary). Then, please submit your application through the following link:
Forum Presentation Date: July 12, 2022 in San Francisco
Eligibility
All submitters must satisfy the following eligibility constraints:
Dissertation topic must be relevant to the DAC community.
Students with at least one published or accepted conference, symposium or journal paper.
Students within 1-2 years of dissertation completion and students who have completed their dissertation during the 2021-2022 academic year. Students closer to graduation will have higher priority since the rest of the students can attend a future Ph.D. Forum with more mature results.
Students who have presented previously at the DATE and ASP-DAC Ph.D. forums are eligible, but will be less likely to receive travel assistance.
Previous DAC SIGDA Ph.D. forum presenters are not eligible.
Students having a conflict of interests with one of the (co-)chairs and/or a member of the evaluation committee are allowed to submit. The submission will then be handled by different chairs/members and the entire evaluation will be completely blind to the anyone with a CoI.
Furthermore, it is strongly recommended to consider the following remarks:
The abstract is the key part of your submission. Write the abstract for someone familiar with your technical area, but entirely unfamiliar with your work. Clearly indicate the motivation of your Ph.D. dissertation topic, the uniqueness of your approach, as well as the potential impact your approach may have on the topic.
Proper spelling, grammar, and coherent organization are critical: remember that the two pages may be the only information about yourself and your PhD research available to the reviewers.
Travel Support and Best Presentation Award
All presentations selected to be presented at the DAC Ph.D. Forum are eligible to apply for some travel support as well as for getting awarded with a Best Presentation Award. Corresponding information on how to apply for travel support will be provided later to all accepted presenters (however, please note that travel support can only be given to a selected amount of presenters and will only cover a fraction of the actually needed travel costs). The Best Presentation Award is selected by a dedicated committee at the Ph.D. Forum (taking the submission as well as the actual presentation into account). The same CoI guidelines as for submission evaluation apply.
Contact
For questions not addressed on this page, please send an e-mail to Robert Wille (robert.wille@jku.at). Please include “DAC Ph.D Forum” in the subject line of your email.
ACM SIGDA/IEEE CEDA Ph.D. Forum at DAC 2021 is virtually co-located with DAC’21.
Program
Session I – December 6, 2021 10AM-11AM Pacific Time
1.1
M.SALAH: Mechanism for Simulation-Assisted Layout PArtitioning and Analysis of Hotspots
Sherif Mousa
1.2
Fully Automated High Power Amplifier Design: From Transistor Selection to Post-layout Generation
Lida Kouhalvandi
1.3
Designing Data-Aware Network-on-Chip for Performance
Abhijit Das
1.4
Pre and Post Silicon Verification Techniques for Analog and Mixed Signal Circuits
Sayandeep Sanyal
1.5
Ultra-Fast Temperature Estimation Methods for Architecture-Level Thermal Modeling
Hameedah Sultan
1.6
Hardware-Software Co-Design for Emerging Workloads
Diksha Moolchandani
1.7
Leakage Aware Dynamic Thermal Management for 3D Memory Architectures
Lokesh Siddhu
1.8
Architectural-Space Exploration of Energy-Efficient Approximate Arithmetic Units for Error-Tolerant Applications
Haroon Waris
1.9
Novel Attack and Defense Strategies for Enahcned Logic Locking Security
Lilas Alrahis
Session II – December 6, 2021 11AM-Noon Pacific Time
2.1
Proving Correctness of Industrial Multipliers using Symbolic Computer Algebra
Alireza Mahzoon
2.2
Resilience and Energy-Efficiency for Deep Learning and Spiking Neural Networks for Embedded Systems
Rachmad Vidya Wicaksana Putra
2.3
Robust and Energy-Efficient Deep Learning Systems
Muhammad Abdullah Hanif
2.4
Personalized Deep Learning for Patient-Specific Physiological Monitoring in IoT
Zhenge Jia
2.5
Network-on-Chip Performance Analysis and Optimization for Deep Learning Applications
Sumit Kumar Mandal
2.6
Efficient, Mixed Precision In-Memory Deep learning at the Edge
Shamma Nasrin
2.7
Design of ML-based and Open Source EDA for Power Delivery Network Synthesis and Analysis
Vidya A. Chhabria
2.8
Cross-Layer Techniques for Energy-Efficiency and Resiliency of Advanced Machine Learning Architectures
Alberto Marchisio
2.9
Machine Learning Algorithms in Electronics Design Automation
Zhiyao Xie
2.10
Efficient Stochastic Computing Machine Learning Acceleration at the Edge
Wojciech Romaszkan
Session III – December 6, 2021 12PM-1PM Pacific Time
3.1
Designing Obfuscated Systems for Enhanced Hardware-Oriented Security
Michael Zuzak
3.2
Designing Approximate Accelerators, Automatically
Jorge Castro-Godínez
3.3
Breaking the Energy Cage of Insect-scale Autonomous Drones: Interplay of Probabilistic Hardware and Co-designed Algorithms
Priyesh Shukla
3.4
Modeling and Optimization of Next-Generation AI Accelerators under Uncertainties
Sanmitra Banerjee
3.5
Hardware-Software Codesign of Silicon Photonic AI Accelerators
Febin Sunny
3.6
High-performance Spectral Methods for Hypergraphs
Ali Aghdaei
3.7
Low-Power Unary Computing Architecture
Di Wu
3.8
Intrinsic Authentication at IoT Edge Nodes using Spatial and Temporal Signatures
Ahish Shylendra
3.9
Secure and Usable Zero-interaction Pairing and Authentication Methods for the Internet-of-Things
Kyuin Lee
3.10
Energy-Quality Scalable Hardware and Software Solutions for Energy-Efficient Approximate Computing
Setareh Behroozi
Eligibility
Dissertation topic must be relevant to the DAC community.
Students with at least one published or accepted conference, symposium or journal paper.
Students within 1-2 years of dissertation completion and students who have completed their dissertation during the 2020-2021 academic year. Students closer to graduation will have higher priority since the rest of the students can attend a future Ph.D. Forum with more mature results.
Students who have presented previously at the DATE and ASP-DAC Ph.D. forums are eligible, but will be less likely to receive travel assistance.
Previous DAC SIGDA Ph.D. forum presenters are not eligible.
A two-page PDF abstract of the dissertation (in two-column format, using 10-11 pt. fonts and single-spaced lines), including name, institution, advisor, contact information, estimated (or actual) graduation date, whether the work has been presented at ASP-DAC Ph.D. Forum or DATE Ph.D. Forum, as well as figures, and bibliography (if applicable). The two-page limit on the abstract will be strictly enforced: any material beyond the second page will be truncated before sending to the reviewers. Please include a description of the supporting paper, including the publication forum. A list of all papers authored or co-authored by the student, related to the dissertation topic and included in the two-page abstract, will strengthen the submission.
A published (or accepted) paper, in support of the submitted dissertation abstract. The paper must be related to the dissertation topic and the publication forum must have a valid ISBN number. It will be helpful, but is not required, to include your name and the publication forum on the first page of the paper. Papers on topics unrelated to the dissertation abstract or not yet accepted will not be considered during the review process.
Please Note:
The abstract is the key part of your submission. Write the abstract for someone familiar with your technical area, but entirely unfamiliar with your work. Clearly indicate the motivation of your Ph.D. dissertation topic, the uniqueness of your approach, as well as the potential impact your approach may have on the topic.
In the beginning of the abstract, please indicate to which track your submission belongs to.
Proper spelling, grammar, and coherent organization are critical: remember that the two pages may be the only information about yourself and your PhD research available to the reviewers.
All submissions must be made electronically.
Please include the supporting paper with the abstract in one PDF file and submit the single file. There are many free utilities available online which can merge multiple PDF files into a single file if necessary.
Topics of Interest (not limited by)
System-level Design, Synthesis and Optimization (including network-on-chip, system-on-chip and multi/many-core, HW/SW co-design, embedded software issues, modeling and simulation)
Internet of Things (IoT)
Autonomous Systems
High Level Synthesis, Logic Level Synthesis
Power and Reliability Analysis and Optimization (including power management from system level to circuit level, thermal management, process variability management)
Timing Analysis, Circuit and Interconnect Simulation
Physical Design and Manufacturability
Signal Integrity and Design Reliability
Verification, Testing, Pre- and Post-Silicon Validation, Failure Analysis
For questions not addressed on this page, please send e-mail to Dr. Topaloglu (rasit@us.ibm.com). Please include “DAC Ph.D Forum” in the subject line of your email.
Organizing Committee
Rasit Topaloglu, IBM (Chair)
Iris Hui-Ru Jiang, National Taiwan University
Robert Wille, Johannes Kepler University, Linz
Jingtong Hu (SIGDA Representative), University of Pittsburgh
Program Committee
Cristinel
Ababei
Marquette University
Raid
Ayoub
Intel
Ateet
Bhalla
Independent Technology Consultant, India
Rajat Subhra
Chakraborty
Associate Professor, Dept. of CSE, IIT Kharagpur
Xiaoming
Chen
Institute of Computing Technology, Chinese Academy of Sciences
Li
Du
University of California, Los Angeles
Shao-Yun
Fang
National Taiwan University of Science and Technology
Hui-Ru
Jiang
National Taiwan University
Jinwook
Jung
IBM
Ryan
Kim
Colorado State University
Myung-Chul
Kim
Google
Younghyun
Kim
University of Wisconsin-Madison
Bing
Li
Technical University of Munich
Preeti
Panda
Indian Institute of Technology Delhi
Sudeep
Pasricha
Colorado State University
Rahul
Rao
IBM
Emre
Salman
Stony Brook University
Hassan
Salmani
Howard University
Korkut
Tokgoz
Tokyo Institute of Technology
Rasit Onur
Topaloglu
IBM
Miroslav
Velev
Aries Design Automation
Robert
Wille
Johannes Kepler University Linz
Hua
Xiang
IBM
Jiang
Xu
Hong Kong Universtiy of Science and Technology
Cindy Yang
Yi
Virginia Tech
Wei
Zhang
The Hong Kong University of Science and Technology
We are thrilled to announce Design Automation WebiNar (DAWN) to drive research momentum and ensure our community remains at the cutting edge. Different from conventional keynote and individual speaker webinars, DAWN is a special-session-style webinar. DAWN is formed by multiple presentations on focused topics by leading experts in our community.
Problem 1: Circuit Design and Analysis Contributed by Jianlei Yang, Beihang University Overview: Solve Landau-Lifshitz-Gilbert (LLG) equation (in C++) Reference: Iwasaki, Junichi, Masahito Mochizuki, and Naoto Nagaosa. “Current-induced skyrmion dynamics in constricted geometries,” Nature nanotechnology 8.10 (2013): 742.
Problem 2: Physical Design & Design for Manufacturability Contributed by William Chow, Cadence Overview: Tap assignment for gated clock network (in C++) Reference: W-H Chen, C-K Wang, H-M Chen, Y-C Chou, and C-H Tsai, “A Comparative Study on Multisource Clock Network Synthesis,” The 22nd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 2016
Problem 3: Logic & High-Level Synthesis Overview: Boolean Function Manipulation by Quantification (in C++) Reference: No specific reference is provided.
Problem 4: System Design & Analysis Contributed by Andy Yu-Guang Chen, National Central University Overview: On-line Wake-up Scheduling for Multi-module design (in C++) Reference 1: D. Brelaz, “New Methods to Color the Vertices of a Graph,” Communications of the ACM, Vol.22, Issue 4, Apr. 1979. Reference 2: M.C. Lee, Y. Shi, Y.G. Chen, D. Marculescu, S.C. Chang, “Efficient On-Line Module-Level Wake-Up Scheduling for High Performance Multi-Module Designs,” Proc. on the International Symposium on Physical Design (ISPD), 2012, Page(s): 97-104.
Problem 5: Functional Verification & Testing Contributed by Hao Zheng, University of South Florida Overview: Cycle-based logic simulation (in C++) Reference 1: S. Palnitkar and D. Parham, “Cycle Simulation Techniques,” IEEE International Verilog HDL Conference, 1995, Page(s) 2-8. Reference 2: A. Biere, “The AIGER And-Inverter Graph (AIG) Format, Version 20070427,” Johannes Kepler University, 2006-2007
Problem 6: Future technologies (Bio-EDA, Security, AI, etc.) Contributed by Mimi Xie, The University of Texas at San Antonio and Caiwen Ding, University of Connecticut Overview: Efficient Pruning for Neural Networks (in Python) Reference: Han, Song, Jeff Pool, John Tran, and William Dally. “Learning both weights and connections for efficient neural network,” In Advances in neural information processing systems, pp. 1135-1143. 2015.
DAC Award Ceremony on July 13, 2023.
